From 200ac0ef87d3d076ccd5d738e4d1acb7f7b2879f Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 20 Jun 2012 11:57:12 +0000 Subject: target-arm: Convert performance monitor registers Convert the v7 performance monitor cp15 registers to the new scheme. Signed-off-by: Peter Maydell --- target-arm/translate.c | 26 +------------------------- 1 file changed, 1 insertion(+), 25 deletions(-) (limited to 'target-arm/translate.c') diff --git a/target-arm/translate.c b/target-arm/translate.c index e6b0d87..f4e9435 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2439,30 +2439,6 @@ static int disas_dsp_insn(CPUARMState *env, DisasContext *s, uint32_t insn) return 1; } -static int cp15_user_ok(CPUARMState *env, uint32_t insn) -{ - int cpn = (insn >> 16) & 0xf; - int cpm = insn & 0xf; - int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38); - - if (arm_feature(env, ARM_FEATURE_V7) && cpn == 9) { - /* Performance monitor registers fall into three categories: - * (a) always UNDEF in usermode - * (b) UNDEF only if PMUSERENR.EN is 0 - * (c) always read OK and UNDEF on write (PMUSERENR only) - */ - if ((cpm == 12 && (op < 6)) || - (cpm == 13 && (op < 3))) { - return env->cp15.c9_pmuserenr; - } else if (cpm == 14 && op == 0 && (insn & ARM_CP_RW_BIT)) { - /* PMUSERENR, read only */ - return 1; - } - return 0; - } - return 0; -} - /* Disassemble system coprocessor (cp15) instruction. Return nonzero if instruction is not defined. */ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn) @@ -2487,7 +2463,7 @@ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn) return 1; } - if (IS_USER(s) && !cp15_user_ok(env, insn)) { + if (IS_USER(s)) { return 1; } -- cgit v1.1