From 959082fc4a93a016a6b697e1e0c2b373d8a3a373 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 17 Sep 2015 14:25:46 -0700 Subject: target-*: Increment num_insns immediately after tcg_gen_insn_start This does tidy the icount test common to all targets. Reviewed-by: Aurelien Jarno Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target-arm/translate-a64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'target-arm/translate-a64.c') diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 6a66ac0..4670941 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -11104,8 +11104,9 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(dc->pc); + num_insns++; - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } @@ -11120,7 +11121,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns == 0); + assert(num_insns == 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); dc->is_jmp = DISAS_EXC; @@ -11139,7 +11140,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - num_insns++; } while (!dc->is_jmp && !tcg_op_buf_full() && !cs->singlestep_enabled && !singlestep && -- cgit v1.1