From ec7b4ce4c7864337a336721721d48456b4b5b51d Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Fri, 29 Aug 2014 15:00:29 +0100 Subject: target-arm: Implement pmccntr_sync function This is used to synchronise the PMCCNTR counter and swap its state between enabled and disabled if required. It must always be called twice, both before and after any logic that could change the state of the PMCCNTR counter. Signed-off-by: Alistair Francis Signed-off-by: Peter Crosthwaite Message-id: 62811d4c0f7b1384f7aab62ea2fcfda3dcb0db50.1409025949.git.peter.crosthwaite@xilinx.com [PMM: fixed minor typos in pmccntr_sync doc comment] Signed-off-by: Peter Maydell --- target-arm/cpu.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'target-arm/cpu.h') diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 60dea03..51bedc8 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -353,6 +353,17 @@ int cpu_arm_signal_handler(int host_signum, void *pinfo, int arm_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int mmu_idx); +/** + * pmccntr_sync + * @env: CPUARMState + * + * Synchronises the counter in the PMCCNTR. This must always be called twice, + * once before any action that might affect the timer and again afterwards. + * The function is used to swap the state of the register if required. + * This only happens when not in user mode (!CONFIG_USER_ONLY) + */ +void pmccntr_sync(CPUARMState *env); + /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants * for both old and new bit meanings. Code which tests against those -- cgit v1.1