From b85a1fd61c4d72c7928cd9b70f9f59fb2895936d Mon Sep 17 00:00:00 2001 From: Fabian Aggeler Date: Thu, 11 Dec 2014 12:07:50 +0000 Subject: target-arm: make CSSELR banked Rename CSSELR (cache size selection register) and add secure instance (AArch32). Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell Message-id: 1416242878-876-16-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell --- target-arm/cpu.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'target-arm/cpu.h') diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6559aa8..f06d209 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -177,7 +177,15 @@ typedef struct CPUARMState { /* System control coprocessor (cp15) */ struct { uint32_t c0_cpuid; - uint64_t c0_cssel; /* Cache size selection. */ + union { /* Cache size selection */ + struct { + uint64_t _unused_csselr0; + uint64_t csselr_ns; + uint64_t _unused_csselr1; + uint64_t csselr_s; + }; + uint64_t csselr_el[4]; + }; union { /* System control register. */ struct { uint64_t _unused_sctlr; -- cgit v1.1