From a4af30447b20b4140133edb90dd0478099cac511 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 19 Mar 2014 09:35:19 -0700 Subject: target-alpha: Convert opcode 0x1F to source/sink Signed-off-by: Richard Henderson --- target-alpha/translate.c | 30 ++++++++++-------------------- 1 file changed, 10 insertions(+), 20 deletions(-) (limited to 'target-alpha') diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 3c198eb..519ccf3 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -2992,40 +2992,33 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) #else goto invalid_opc; #endif + case 0x1F: /* HW_ST (PALcode) */ #ifndef CONFIG_USER_ONLY REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); { - TCGv addr, val; - addr = tcg_temp_new(); - if (rb != 31) { - tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); - } else { - tcg_gen_movi_i64(addr, disp12); - } - if (ra != 31) { - val = cpu_ir[ra]; - } else { - val = tcg_temp_new(); - tcg_gen_movi_i64(val, 0); - } + TCGv addr = tcg_temp_new(); + va = load_gpr(ctx, ra); + vb = load_gpr(ctx, rb); + + tcg_gen_addi_i64(addr, vb, disp12); switch ((insn >> 12) & 0xF) { case 0x0: /* Longword physical access */ - gen_helper_stl_phys(cpu_env, addr, val); + gen_helper_stl_phys(cpu_env, addr, va); break; case 0x1: /* Quadword physical access */ - gen_helper_stq_phys(cpu_env, addr, val); + gen_helper_stq_phys(cpu_env, addr, va); break; case 0x2: /* Longword physical access with lock */ - gen_helper_stl_c_phys(val, cpu_env, addr, val); + gen_helper_stl_c_phys(dest_gpr(ctx, ra), cpu_env, addr, va); break; case 0x3: /* Quadword physical access with lock */ - gen_helper_stq_c_phys(val, cpu_env, addr, val); + gen_helper_stq_c_phys(dest_gpr(ctx, ra), cpu_env, addr, va); break; case 0x4: /* Longword virtual access */ @@ -3064,9 +3057,6 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) /* Invalid */ goto invalid_opc; } - if (ra == 31) { - tcg_temp_free(val); - } tcg_temp_free(addr); break; } -- cgit v1.1