From 9e80202352dd49bdd9e67b8b906d86f058431505 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 11 May 2019 15:12:49 -0500 Subject: Initial import of abandoned HQEMU version 2.5.2 --- .../board/xilinx/ppc405-generic/xparameters.h | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 src/roms/u-boot/board/xilinx/ppc405-generic/xparameters.h (limited to 'src/roms/u-boot/board/xilinx/ppc405-generic/xparameters.h') diff --git a/src/roms/u-boot/board/xilinx/ppc405-generic/xparameters.h b/src/roms/u-boot/board/xilinx/ppc405-generic/xparameters.h new file mode 100644 index 0000000..f0ff78f --- /dev/null +++ b/src/roms/u-boot/board/xilinx/ppc405-generic/xparameters.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * based on xparameters-ml507.h by Xilinx + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef XPARAMETER_H +#define XPARAMETER_H + +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 +#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_SPI_0_BASEADDR 0x83400000 +#define XPAR_UARTLITE_0_BASEADDR 0x84000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 +#define XPAR_UARTLITE_0_BAUDRATE 9600 +#define XPAR_SPI_0_NUM_TRANSFER_BITS 8 + +#endif -- cgit v1.1