From d92fa2dc6e42e8bd8470e69d85141176f98feaea Mon Sep 17 00:00:00 2001 From: Le Tan Date: Sat, 16 Aug 2014 13:55:43 +0800 Subject: intel-iommu: add context-cache to cache context-entry Add context-cache to cache context-entry encountered on a page-walk. Each VTDAddressSpace has a member of VTDContextCacheEntry which represents an entry in the context-cache. Since devices with different bus_num and devfn have their respective VTDAddressSpace, this will be a good way to reference the cached entries. Each VTDContextCacheEntry will have a context_cache_gen and the cached entry is valid only when context_cache_gen equals IntelIOMMUState.context_cache_gen. Signed-off-by: Le Tan Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/i386/intel_iommu.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'include') diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index fe1f1e9..d9a5215 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -37,20 +37,40 @@ #define VTD_PCI_DEVFN_MAX 256 #define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) #define VTD_PCI_FUNC(devfn) ((devfn) & 0x07) +#define VTD_SID_TO_BUS(sid) (((sid) >> 8) && 0xff) +#define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff) #define DMAR_REG_SIZE 0x230 #define VTD_HOST_ADDRESS_WIDTH 39 #define VTD_HAW_MASK ((1ULL << VTD_HOST_ADDRESS_WIDTH) - 1) +typedef struct VTDContextEntry VTDContextEntry; +typedef struct VTDContextCacheEntry VTDContextCacheEntry; typedef struct IntelIOMMUState IntelIOMMUState; typedef struct VTDAddressSpace VTDAddressSpace; + +/* Context-Entry */ +struct VTDContextEntry { + uint64_t lo; + uint64_t hi; +}; + +struct VTDContextCacheEntry { + /* The cache entry is obsolete if + * context_cache_gen!=IntelIOMMUState.context_cache_gen + */ + uint32_t context_cache_gen; + struct VTDContextEntry context_entry; +}; + struct VTDAddressSpace { uint8_t bus_num; uint8_t devfn; AddressSpace as; MemoryRegion iommu; IntelIOMMUState *iommu_state; + VTDContextCacheEntry context_cache_entry; }; /* The iommu (DMAR) device state struct */ @@ -82,6 +102,8 @@ struct IntelIOMMUState { uint64_t cap; /* The value of capability reg */ uint64_t ecap; /* The value of extended capability reg */ + uint32_t context_cache_gen; /* Should be in [1,MAX] */ + MemoryRegionIOMMUOps iommu_ops; VTDAddressSpace **address_spaces[VTD_PCI_BUS_MAX]; }; -- cgit v1.1