From e0bcb9ca36e4f3081c7e6841283646985ed9676b Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 2 Feb 2010 19:39:11 +0100 Subject: sh7750: handle MMUCR TI bit When the MMUCR TI bit is set, all the UTLB and ITLB entries should be flushed. Signed-off-by: Aurelien Jarno --- hw/sh7750.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'hw') diff --git a/hw/sh7750.c b/hw/sh7750.c index 933bbc0..9c39f4b 100644 --- a/hw/sh7750.c +++ b/hw/sh7750.c @@ -396,8 +396,11 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr, portb_changed(s, temp); return; case SH7750_MMUCR_A7: - s->cpu->mmucr = mem_value; - return; + if (mem_value & MMUCR_TI) { + cpu_sh4_invalidate_tlb(s->cpu); + } + s->cpu->mmucr = mem_value & ~MMUCR_TI; + return; case SH7750_PTEH_A7: /* If asid changes, clear all registered tlb entries. */ if ((s->cpu->pteh & 0xff) != (mem_value & 0xff)) -- cgit v1.1