From 27013bf20d5d93ac75d398aa3608604e8ad91b5a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 21 Aug 2013 18:36:35 +0200 Subject: a15mpcore: Use qemu_get_cpu() for generic timers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This simplifies the loop and aids with refactoring of CPU list. Requested-by: Peter Maydell Signed-off-by: Andreas Färber --- hw/cpu/a15mpcore.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'hw') diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index af182da..9abba67 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -50,7 +50,6 @@ static int a15mp_priv_init(SysBusDevice *dev) SysBusDevice *busdev; const char *gictype = "arm_gic"; int i; - CPUState *cpu; if (kvm_irqchip_in_kernel()) { gictype = "kvm-arm-gic"; @@ -72,8 +71,8 @@ static int a15mp_priv_init(SysBusDevice *dev) /* Wire the outputs from each CPU's generic timer to the * appropriate GIC PPI inputs */ - for (i = 0, cpu = first_cpu; i < s->num_cpu; i++, cpu = cpu->next_cpu) { - DeviceState *cpudev = DEVICE(cpu); + for (i = 0; i < s->num_cpu; i++) { + DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); int ppibase = s->num_irq - 32 + i * 32; /* physical timer; we wire it up to the non-secure timer's ID, * since a real A15 always has TrustZone but QEMU doesn't. -- cgit v1.1 From bdc44640cb33c90809376a262df871a1144d339a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 24 Jun 2013 23:50:24 +0200 Subject: cpu: Use QTAILQ for CPU list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce CPU_FOREACH(), CPU_FOREACH_SAFE() and CPU_NEXT() shorthand macros. Signed-off-by: Andreas Färber --- hw/arm/boot.c | 2 +- hw/i386/kvm/clock.c | 2 +- hw/i386/kvmvapic.c | 2 +- hw/i386/pc.c | 3 +-- hw/ppc/e500.c | 2 +- hw/ppc/ppc.c | 2 +- hw/ppc/spapr.c | 4 ++-- hw/ppc/spapr_hcall.c | 4 ++-- 8 files changed, 10 insertions(+), 11 deletions(-) (limited to 'hw') diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 2cbeefd..1e313af 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -468,7 +468,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) } info->is_linux = is_linux; - for (; cs; cs = cs->next_cpu) { + for (; cs; cs = CPU_NEXT(cs)) { cpu = ARM_CPU(cs); cpu->env.boot_info = info; qemu_register_reset(do_cpu_reset, cpu); diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c index e89e2f7..92aabb8 100644 --- a/hw/i386/kvm/clock.c +++ b/hw/i386/kvm/clock.c @@ -59,7 +59,7 @@ static void kvmclock_vm_state_change(void *opaque, int running, if (!cap_clock_ctrl) { return; } - for (cpu = first_cpu; cpu != NULL; cpu = cpu->next_cpu) { + CPU_FOREACH(cpu) { ret = kvm_vcpu_ioctl(cpu, KVM_KVMCLOCK_CTRL, 0); if (ret) { if (ret != -EINVAL) { diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 15beb80..d3a6fbe 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -498,7 +498,7 @@ static void vapic_enable_tpr_reporting(bool enable) X86CPU *cpu; CPUX86State *env; - for (cs = first_cpu; cs != NULL; cs = cs->next_cpu) { + CPU_FOREACH(cs) { cpu = X86_CPU(cs); env = &cpu->env; info.apic = env->apic_state; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 3a620a1..0c313fe 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -191,13 +191,12 @@ static void pic_irq_request(void *opaque, int irq, int level) DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); if (env->apic_state) { - while (cs) { + CPU_FOREACH(cs) { cpu = X86_CPU(cs); env = &cpu->env; if (apic_accept_pic_intr(env->apic_state)) { apic_deliver_pic_intr(env->apic_state, level); } - cs = cs->next_cpu; } } else { if (level) { diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 9059ff9..cfdd84b 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -540,7 +540,7 @@ static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params, return NULL; } - for (cs = first_cpu; cs != NULL; cs = cs->next_cpu) { + CPU_FOREACH(cs) { if (kvm_openpic_connect_vcpu(dev, cs)) { fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", __func__); diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 59b41cb..bf2d3d4 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -443,7 +443,7 @@ void ppce500_set_mpic_proxy(bool enabled) { CPUState *cs; - for (cs = first_cpu; cs != NULL; cs = cs->next_cpu) { + CPU_FOREACH(cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); cpu->env.mpic_proxy = enabled; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 04f0ee3..8c6e296 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -187,7 +187,7 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) assert(spapr->cpu_model); - for (cpu = first_cpu; cpu != NULL; cpu = cpu->next_cpu) { + CPU_FOREACH(cpu) { uint32_t associativity[] = {cpu_to_be32(0x5), cpu_to_be32(0x0), cpu_to_be32(0x0), @@ -351,7 +351,7 @@ static void *spapr_create_fdt_skel(const char *cpu_model, /* This is needed during FDT finalization */ spapr->cpu_model = g_strdup(modelname); - for (cs = first_cpu; cs != NULL; cs = cs->next_cpu) { + CPU_FOREACH(cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 89e6a00..f10ba8a 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -679,7 +679,7 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr, switch (mflags) { case H_SET_MODE_ENDIAN_BIG: - for (cs = first_cpu; cs != NULL; cs = cs->next_cpu) { + CPU_FOREACH(cs) { PowerPCCPU *cp = POWERPC_CPU(cs); CPUPPCState *env = &cp->env; env->spr[SPR_LPCR] &= ~LPCR_ILE; @@ -688,7 +688,7 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr, break; case H_SET_MODE_ENDIAN_LITTLE: - for (cs = first_cpu; cs != NULL; cs = cs->next_cpu) { + CPU_FOREACH(cs) { PowerPCCPU *cp = POWERPC_CPU(cs); CPUPPCState *env = &cp->env; env->spr[SPR_LPCR] |= LPCR_ILE; -- cgit v1.1 From 38fcbd3f08375eb2986b9b63ccd4f593e71aa99d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 7 Jul 2013 19:50:23 +0200 Subject: cpu: Replace qemu_for_each_cpu() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It was introduced to loop over CPUs from target-independent code, but since commit 182735efaf956ccab50b6d74a4fed163e0f35660 target-independent CPUState is used. A loop can be considered more efficient than function calls in a loop, and CPU_FOREACH() hides implementation details just as well, so use that instead. Suggested-by: Markus Armbruster Acked-by: Michael S. Tsirkin Signed-off-by: Andreas Färber --- hw/acpi/piix4.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) (limited to 'hw') diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 613d987..0b8d1d9 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -667,22 +667,14 @@ static void piix4_cpu_added_req(Notifier *n, void *opaque) piix4_cpu_hotplug_req(s, CPU(opaque), PLUG); } -static void piix4_init_cpu_status(CPUState *cpu, void *data) -{ - CPUStatus *g = (CPUStatus *)data; - CPUClass *k = CPU_GET_CLASS(cpu); - int64_t id = k->get_arch_id(cpu); - - g_assert((id / 8) < PIIX4_PROC_LEN); - g->sts[id / 8] |= (1 << (id % 8)); -} - static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, PCIHotplugState state); static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, PCIBus *bus, PIIX4PMState *s) { + CPUState *cpu; + memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, "acpi-gpe0", GPE_LEN); memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); @@ -693,7 +685,13 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, &s->io_pci); pci_bus_hotplug(bus, piix4_device_hotplug, DEVICE(s)); - qemu_for_each_cpu(piix4_init_cpu_status, &s->gpe_cpu); + CPU_FOREACH(cpu) { + CPUClass *cc = CPU_GET_CLASS(cpu); + int64_t id = cc->get_arch_id(cpu); + + g_assert((id / 8) < PIIX4_PROC_LEN); + s->gpe_cpu.sts[id / 8] |= (1 << (id % 8)); + } memory_region_init_io(&s->io_cpu, OBJECT(s), &cpu_hotplug_ops, s, "acpi-cpu-hotplug", PIIX4_PROC_LEN); memory_region_add_subregion(parent, PIIX4_PROC_BASE, &s->io_cpu); -- cgit v1.1