From 6619bc5c55c1322a89009e2edd530113da95d551 Mon Sep 17 00:00:00 2001 From: Beniamino Galvani Date: Tue, 25 Mar 2014 19:22:10 +0100 Subject: allwinner-emac: update irq status after writes to interrupt registers The irq line status must be updated after writes to the INT_CTL and INT_STA registers. Signed-off-by: Beniamino Galvani Reviewed-by: Peter Crosthwaite Message-id: 1395771730-16882-8-git-send-email-b.galvani@gmail.com Signed-off-by: Peter Maydell --- hw/net/allwinner_emac.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'hw') diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c index 91931ac..d780ba0 100644 --- a/hw/net/allwinner_emac.c +++ b/hw/net/allwinner_emac.c @@ -391,9 +391,11 @@ static void aw_emac_write(void *opaque, hwaddr offset, uint64_t value, break; case EMAC_INT_CTL_REG: s->int_ctl = value; + aw_emac_update_irq(s); break; case EMAC_INT_STA_REG: s->int_sta &= ~value; + aw_emac_update_irq(s); break; case EMAC_MAC_MADR_REG: s->phy_target = value; -- cgit v1.1