From e0dfe5b18919a6a4deb841dcf3212e3e998c95e5 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 21 Jan 2013 15:53:53 +0000 Subject: openpic: add basic support for MPIC v4.2 Besides the new value in the version register, this provides: - ILR support, which includes: - IDR becoming a pure CPU bitmap, allowing 32 CPUs - machine check output support (though other parts of QEMU need to be fixed for it to do something other than immediately reboot the guest) - dummy error interrupt support (EISR0/EIMR0 read as zero) - actually all FSL MPICs get all summary registers returning zero for now, which includes EISR0/EIMR0 Various refactoring is done to support these changes and to ease new functionality (e.g. a more flexible way of declaring regions). Just as the code was already not a full implementation of MPIC v2.0, this is not a full implementation of MPIC v4.2 -- e.g. it still has only one bank of MSIs. Signed-off-by: Scott Wood Signed-off-by: Alexander Graf --- hw/openpic.h | 1 + 1 file changed, 1 insertion(+) (limited to 'hw/openpic.h') diff --git a/hw/openpic.h b/hw/openpic.h index e226d7b..9dcaf0e 100644 --- a/hw/openpic.h +++ b/hw/openpic.h @@ -13,5 +13,6 @@ enum { #define OPENPIC_MODEL_RAVEN 0 #define OPENPIC_MODEL_FSL_MPIC_20 1 +#define OPENPIC_MODEL_FSL_MPIC_42 2 #endif /* __OPENPIC_H__ */ -- cgit v1.1