From d96e1737696974efb4566741e75a1f99920f262b Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Fri, 7 Oct 2011 09:19:37 +0200 Subject: pc: Fix and clean up PIC-to-APIC IRQ path The master PIC is connected to the LINTIN0 of the APICs. As the APIC currently does not track the state of that line, we have to ask the PIC to reinject its IRQ after the CPU picked up an event from the APIC. This introduces pic_get_output to read the master PIC IRQ line state without changing it. The APIC uses this function to decide if a PIC IRQ should be reinjected on apic_update_irq. This reflects better how the real hardware works. The patch fixes some failures of the kvm unit tests apic and eventinj by allowing to enable the proper CPU IRQ deassertion when the guest masks some pending IRQs at PIC level. Signed-off-by: Jan Kiszka Signed-off-by: Blue Swirl --- hw/i8259.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'hw/i8259.c') diff --git a/hw/i8259.c b/hw/i8259.c index e5323ff..6006123 100644 --- a/hw/i8259.c +++ b/hw/i8259.c @@ -146,8 +146,7 @@ static int pic_get_irq(PicState *s) /* raise irq to CPU if necessary. must be called every time the active irq may change */ -/* XXX: should not export it, but it is needed for an APIC kludge */ -void pic_update_irq(PicState2 *s) +static void pic_update_irq(PicState2 *s) { int irq2, irq; @@ -174,14 +173,9 @@ void pic_update_irq(PicState2 *s) printf("pic: cpu_interrupt\n"); #endif qemu_irq_raise(s->parent_irq); - } - -/* all targets should do this rather than acking the IRQ in the cpu */ -#if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA) - else { + } else { qemu_irq_lower(s->parent_irq); } -#endif } #ifdef DEBUG_IRQ_LATENCY @@ -441,6 +435,11 @@ uint32_t pic_intack_read(PicState2 *s) return ret; } +int pic_get_output(PicState2 *s) +{ + return (pic_get_irq(&s->pics[0]) >= 0); +} + static void elcr_ioport_write(void *opaque, target_phys_addr_t addr, uint64_t val, unsigned size) { -- cgit v1.1