From 306a571a2d75e32cd2eae5486c2714b7b7792a63 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 2 May 2012 16:49:40 +0000 Subject: hw/arm_gic: Add qdev property for GIC revision GIC behaviour can be different between revision 1 and 2 of the architectural GIC specification; we also have to handle the legacy 11MPCore GIC, which is different again in some places. Introduce a qdev property so we can behave appropriately. Signed-off-by: Peter Maydell --- hw/arm_gic.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'hw/arm_gic.c') diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 2ec10ce..ad72ac6 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -119,8 +119,13 @@ typedef struct gic_state struct gic_state *backref[NCPU]; MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */ uint32_t num_irq; + uint32_t revision; } gic_state; +/* The special cases for the revision property: */ +#define REV_11MPCORE 0 +#define REV_NVIC 0xffffffff + static inline int gic_get_current_cpu(gic_state *s) { if (s->num_cpu > 1) { @@ -880,6 +885,11 @@ static int arm_gic_init(SysBusDevice *dev) static Property arm_gic_properties[] = { DEFINE_PROP_UINT32("num-cpu", gic_state, num_cpu, 1), DEFINE_PROP_UINT32("num-irq", gic_state, num_irq, 32), + /* Revision can be 1 or 2 for GIC architecture specification + * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC. + * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".) + */ + DEFINE_PROP_UINT32("revision", gic_state, revision, 1), DEFINE_PROP_END_OF_LIST(), }; -- cgit v1.1