From a316d3353cefb6634f8007c8bb18f4744a66766b Mon Sep 17 00:00:00 2001 From: bellard Date: Sun, 20 Nov 2005 10:32:34 +0000 Subject: added CPU_COMMON and CPUState.tb_jmp_cache[] git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1630 c046a42c-6fe2-441c-8c8c-71466251a162 --- cpu-defs.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'cpu-defs.h') diff --git a/cpu-defs.h b/cpu-defs.h index 912133e..fb4f8e8 100644 --- a/cpu-defs.h +++ b/cpu-defs.h @@ -77,6 +77,9 @@ typedef unsigned long ram_addr_t; #define MAX_BREAKPOINTS 32 +#define TB_JMP_CACHE_BITS 12 +#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) + #define CPU_TLB_SIZE 256 typedef struct CPUTLBEntry { @@ -91,4 +94,30 @@ typedef struct CPUTLBEntry { target_phys_addr_t addend; } CPUTLBEntry; +#define CPU_COMMON \ + struct TranslationBlock *current_tb; /* currently executing TB */ \ + /* soft mmu support */ \ + /* in order to avoid passing too many arguments to the memory \ + write helpers, we store some rarely used information in the CPU \ + context) */ \ + unsigned long mem_write_pc; /* host pc at which the memory was \ + written */ \ + target_ulong mem_write_vaddr; /* target virtual addr at which the \ + memory was written */ \ + /* 0 = kernel, 1 = user */ \ + CPUTLBEntry tlb_read[2][CPU_TLB_SIZE]; \ + CPUTLBEntry tlb_write[2][CPU_TLB_SIZE]; \ + struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ + \ + /* from this point: preserved by CPU reset */ \ + /* ice debug support */ \ + target_ulong breakpoints[MAX_BREAKPOINTS]; \ + int nb_breakpoints; \ + int singlestep_enabled; \ + \ + /* user data */ \ + void *opaque; + + + #endif -- cgit v1.1