From d362e757d35727c915052974086f8687d3557431 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Fri, 17 Feb 2012 18:31:17 +0100 Subject: target-i386: Add infrastructure for reporting TPR MMIO accesses This will allow the APIC core to file a TPR access report. Depending on the accelerator and kernel irqchip mode, it will either be delivered right away or queued for later reporting. In TCG mode, we can restart the triggering instruction and can therefore forward the event directly. KVM does not allows us to restart, so we postpone the delivery of events recording in the user space APIC until the current instruction is completed. Note that KVM without in-kernel irqchip will report the address after the instruction that triggered the access. Signed-off-by: Jan Kiszka Signed-off-by: Avi Kivity --- cpu-all.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'cpu-all.h') diff --git a/cpu-all.h b/cpu-all.h index e2c3c49..80e6d42 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -375,8 +375,9 @@ DECLARE_TLS(CPUState *,cpu_single_env); #define CPU_INTERRUPT_TGT_INT_0 0x0100 #define CPU_INTERRUPT_TGT_INT_1 0x0400 #define CPU_INTERRUPT_TGT_INT_2 0x0800 +#define CPU_INTERRUPT_TGT_INT_3 0x2000 -/* First unused bit: 0x2000. */ +/* First unused bit: 0x4000. */ /* The set of all bits that should be masked when single-stepping. */ #define CPU_INTERRUPT_SSTEP_MASK \ -- cgit v1.1