From 3e68482224129c3ddc061af7c9d438b882ecfdd1 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Tue, 3 Nov 2015 17:18:50 -0200 Subject: target-i386: Set "check=off" by default on pc-*-2.4 and older The default CPU model (qemu64) have some issues today: it enables some features (ABM and SSE4a) that are not present in many host CPUs. That means many hosts (but not all of them) had those features silently disabled in the default configuration in QEMU 2.4 and older. With the new "check=on" default, this causes warnings to be printed in the default configuration, because of the lack of SSE4A on all Intel hosts, and the lack of ABM on Sandy Bridge and older hosts: $ qemu-system-x86_64 -machine pc,accel=kvm warning: host doesn't support requested feature: CPUID.80000001H:ECX.abm [bit 5] warning: host doesn't support requested feature: CPUID.80000001H:ECX.sse4a [bit 6] Those issues will be fixed in pc-*-2.5 and newer. But as we can't change the guest ABI in pc-*-2.4, disable "check" mode by default in pc-*-2.4 and older so we don't print spurious warnings. Reviewed-by: Paolo Bonzini Signed-off-by: Eduardo Habkost --- include/hw/i386/pc.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 606dbc2..8be4520 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -322,6 +322,11 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); .driver = "host" "-" TYPE_X86_CPU,\ .property = "host-cache-info",\ .value = "on",\ + },\ + {\ + .driver = TYPE_X86_CPU,\ + .property = "check",\ + .value = "off",\ }, #define PC_COMPAT_2_3 \ -- cgit v1.1 From 0909ad24b2769368716c85f79fbb995dbb7041a9 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Tue, 3 Nov 2015 17:17:33 -0200 Subject: target-i386: Remove SSE4a from qemu64 CPU model SSE4a is not available in any Intel CPU, and we want to make the default CPU runnable in most hosts, so it doesn't make sense to enable it by default in KVM mode. We should eventually have all features supported by TCG enabled by default in TCG mode, but as we don't have a good mechanism today to ensure we have different defaults in KVM and TCG mode, disable SSE4a in the qemu64 CPU model entirely. Reviewed-by: Paolo Bonzini Signed-off-by: Eduardo Habkost --- include/hw/i386/pc.h | 5 +++++ target-i386/cpu.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 8be4520..bc82c14 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -327,6 +327,11 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); .driver = TYPE_X86_CPU,\ .property = "check",\ .value = "off",\ + },\ + {\ + .driver = "qemu64" "-" TYPE_X86_CPU,\ + .property = "sse4a",\ + .value = "on",\ }, #define PC_COMPAT_2_3 \ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 9d0eedf..5aa3ce7 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -676,7 +676,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .features[FEAT_8000_0001_ECX] = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | - CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, + CPUID_EXT3_ABM, .xlevel = 0x8000000A, }, { -- cgit v1.1 From 711956722c6764336f8b78a2106e57c55f02f36d Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Tue, 3 Nov 2015 17:24:18 -0200 Subject: target-i386: Remove ABM from qemu64 CPU model ABM is not available on Sandy Bridge and older, and we want to make the default CPU runnable in most hosts, so it won't be enabled by default in KVM mode. We should eventually have all features supported by TCG enabled by default in TCG mode, but as we don't have a good mechanism today to ensure we have different defaults in KVM and TCG mode, disable ABM in the qemu64 CPU model entirely. Reviewed-by: Paolo Bonzini Signed-off-by: Eduardo Habkost --- include/hw/i386/pc.h | 5 +++++ target-i386/cpu.c | 3 +-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index bc82c14..8b54863 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -332,6 +332,11 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); .driver = "qemu64" "-" TYPE_X86_CPU,\ .property = "sse4a",\ .value = "on",\ + },\ + {\ + .driver = "qemu64" "-" TYPE_X86_CPU,\ + .property = "abm",\ + .value = "on",\ }, #define PC_COMPAT_2_3 \ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 5aa3ce7..90e4529 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -675,8 +675,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .features[FEAT_8000_0001_EDX] = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .features[FEAT_8000_0001_ECX] = - CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | - CPUID_EXT3_ABM, + CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, .xlevel = 0x8000000A, }, { -- cgit v1.1 From 6aa91e4a0237ddcebb85e3a95e166f3b3cfa42ae Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Tue, 3 Nov 2015 17:24:18 -0200 Subject: target-i386: Remove POPCNT from qemu64 and qemu32 CPU models POPCNT is not available on Penryn and older and on Opteron_G2 and older, and we want to make the default CPU runnable in most hosts, so it won't be enabled by default in KVM mode. We should eventually have all features supported by TCG enabled by default in TCG mode, but as we don't have a good mechanism today to ensure we have different defaults in KVM and TCG mode, disable POPCNT in the qemu64 and qemu32 CPU models entirely. Reviewed-by: Paolo Bonzini Signed-off-by: Eduardo Habkost --- include/hw/i386/pc.h | 10 ++++++++++ target-i386/cpu.c | 4 ++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 8b54863..4bbc0ff 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -337,6 +337,16 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); .driver = "qemu64" "-" TYPE_X86_CPU,\ .property = "abm",\ .value = "on",\ + },\ + {\ + .driver = "qemu64" "-" TYPE_X86_CPU,\ + .property = "popcnt",\ + .value = "on",\ + },\ + {\ + .driver = "qemu32" "-" TYPE_X86_CPU,\ + .property = "popcnt",\ + .value = "on",\ }, #define PC_COMPAT_2_3 \ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 90e4529..090d1d8 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -671,7 +671,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, .features[FEAT_1_ECX] = - CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT, + CPUID_EXT_SSE3 | CPUID_EXT_CX16, .features[FEAT_8000_0001_EDX] = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .features[FEAT_8000_0001_ECX] = @@ -771,7 +771,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .features[FEAT_1_EDX] = PPRO_FEATURES, .features[FEAT_1_ECX] = - CPUID_EXT_SSE3 | CPUID_EXT_POPCNT, + CPUID_EXT_SSE3, .xlevel = 0x80000004, }, { -- cgit v1.1 From f7fda280948a5e74aeb076ef346b991ecb173c56 Mon Sep 17 00:00:00 2001 From: Xiao Guangrong Date: Thu, 29 Oct 2015 15:31:39 +0800 Subject: target-i386: Enable clflushopt/clwb/pcommit instructions These instructions are used by NVDIMM drivers and the specification is located at: https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf There instructions are available on Skylake Server. Signed-off-by: Xiao Guangrong Reviewed-by: Richard Henderson Signed-off-by: Eduardo Habkost --- target-i386/cpu.c | 4 ++-- target-i386/cpu.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 090d1d8..0d080c1 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -259,8 +259,8 @@ static const char *svm_feature_name[] = { static const char *cpuid_7_0_ebx_feature_name[] = { "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep", "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL, - "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL, - NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL, + "avx512f", NULL, "rdseed", "adx", "smap", NULL, "pcommit", "clflushopt", + "clwb", NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL, }; static const char *cpuid_apm_edx_feature_name[] = { diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 62f7879..fc4a605 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -576,6 +576,9 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EBX_RDSEED (1U << 18) #define CPUID_7_0_EBX_ADX (1U << 19) #define CPUID_7_0_EBX_SMAP (1U << 20) +#define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ +#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ +#define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ -- cgit v1.1