From 28b027d5b63c7550c7390041d6dd50948c8f55b8 Mon Sep 17 00:00:00 2001 From: Leon Alrae Date: Tue, 14 Apr 2015 10:33:35 +0100 Subject: target-mips: remove misleading comments in translate_init.c PABITS are not hardcoded to 36 bits and we do not model 59 PABITS (which is the architectural limit) in QEMU. Signed-off-by: Leon Alrae Reviewed-by: Aurelien Jarno --- target-mips/translate_init.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 51e7c98..5f0cf9a 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -553,9 +553,6 @@ static const mips_def_t mips_defs[] = (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), .SEGBITS = 42, - /* The architectural limit is 59, but we have hardcoded 36 bit - in some places... - .PABITS = 59, */ /* the architectural limit */ .PABITS = 36, .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, .mmu_type = MMU_TYPE_R4000, @@ -637,9 +634,6 @@ static const mips_def_t mips_defs[] = (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), .SEGBITS = 42, - /* The architectural limit is 59, but we have hardcoded 36 bit - in some places... - .PABITS = 59, */ /* the architectural limit */ .PABITS = 36, .insn_flags = CPU_MIPS64R6, .mmu_type = MMU_TYPE_R4000, @@ -703,9 +697,6 @@ static const mips_def_t mips_defs[] = (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), .SEGBITS = 42, - /* The architectural limit is 59, but we have hardcoded 36 bit - in some places... - .PABITS = 59, */ /* the architectural limit */ .PABITS = 36, .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2, .mmu_type = MMU_TYPE_R4000, -- cgit v1.1