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* tcg-ppc64: Handle deposit of zeroRichard Henderson2013-04-151-6/+16
| | | | | | | | | | The TCG optimizer does great work when inserting constants, being able to fold the open-coded deposit expansion to just an AND or an OR. Avoid a bit the regression caused by having the deposit opcode by expanding deposit of zero as an AND. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Implement mulu2/muls2_i64Richard Henderson2013-04-152-2/+29
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Implement add2/sub2_i64Richard Henderson2013-04-152-2/+58
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Use getauxval for ISA detectionRichard Henderson2013-04-151-0/+14
| | | | | | | | Glibc 2.16 includes an easy way to get feature bits previously buried in /proc or the program startup auxiliary vector. Use it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Implement movcondRichard Henderson2013-04-152-2/+61
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Use ISEL for setcondRichard Henderson2013-04-151-62/+119
| | | | | | | | There are a few simple special cases that should be handled first. Break these out to subroutines to avoid code duplication. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Use MFOCRF instead of MFCRRichard Henderson2013-04-151-4/+8
| | | | | | | | | It takes half the cycles to read one CR register instead of all 8. This is a backward compatible addition to the ISA, so chips prior to Power 2.00 spec will simply continue to read the entire CR register. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Cleanup i32 constants to tcg_out_cmpRichard Henderson2013-04-151-0/+5
| | | | | | | | Nothing else in the call chain ensures that these constants don't have garbage in the high bits. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Use TCGType throughout comparesRichard Henderson2013-04-151-19/+19
| | | | | | | | | | The optimization/bug being fixed is that tcg_out_cmp was not applying the right type to loading a constant, in the case it can't be implemented directly. Rather than recomputing the TCGType enum from the arch64 bool, pass around the original TCGType throughout. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Use I constraint for mulRichard Henderson2013-04-151-12/+12
| | | | | | | | | The mul_i32 pattern was loading non-16-bit constants into a register, when we can get the middle-end to do that for us. The mul_i64 pattern was not considering that MULLI takes 64-bit inputs. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Implement depositRichard Henderson2013-04-152-2/+14
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Handle constant inputs for some compound logicalsRichard Henderson2013-04-151-10/+34
| | | | | | | | Since we have special code to handle and/or/xor with a constant, apply the same to andc/orc/eqv with a constant. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Implement compound logicalsRichard Henderson2013-04-152-10/+44
| | | | | | | Mostly copied from the ppc32 port. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Implement bswap64Richard Henderson2013-04-152-1/+36
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Implement bswap16 and bswap32Richard Henderson2013-04-152-4/+47
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Implement rotatesRichard Henderson2013-04-152-2/+41
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Streamline qemu_ld/st insn selectionRichard Henderson2013-04-151-110/+56
| | | | | | | | Using a table to look up insns of the right width and sign. Include support for the Power 2.06 LDBRX and STDBRX insns. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Use automatic implementation of ext32u_i64Richard Henderson2013-04-152-8/+3
| | | | | | | The enhancements to and immediate obviate this. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Improve and_i64 with constantRichard Henderson2013-04-151-14/+50
| | | | | | | Use RLDICL and RLDICR. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Improve and_i32 with constantRichard Henderson2013-04-152-3/+53
| | | | | | | Use RLWINM Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Tidy or and xor patterns.Richard Henderson2013-04-151-24/+31
| | | | | | | Handle constants in common code; we'll want to reuse that later. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Allow constant first argument to subRichard Henderson2013-04-151-4/+17
| | | | | | | Using SUBFIC for 16-bit signed constants. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Improve constant add and sub ops.Richard Henderson2013-04-151-44/+64
| | | | | | | | | Improve constant addition -- previously we'd emit useless addi with 0. Use new constraints to force the driver to pull full 64-bit constants into a register. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Rearrange integer constant constraintsRichard Henderson2013-04-151-10/+33
| | | | | | | | We'll need a zero, and Z makes more sense for that. Make sure we have a full compliment of signed and unsigned 16 and 32-bit tests. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Cleanup tcg_out_moviRichard Henderson2013-04-151-24/+17
| | | | | | | | | | | The test for using movi32 was sub-optimal for TCG_TYPE_I32, comparing a signed 32-bit quantity against an unsigned 32-bit quantity. When possible, use addi+oris for 32-bit unsigned constants. Otherwise, standardize on addi+oris+ori instead of addis+ori+rldicl. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Fix setcond_i32Richard Henderson2013-04-151-0/+6
| | | | | | | We weren't ignoring the high 32 bits during a NE comparison. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Introduce and use TAI and SAIRichard Henderson2013-04-151-73/+70
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Introduce and use tcg_out_shri64Richard Henderson2013-04-151-2/+7
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Introduce and use tcg_out_shli64Richard Henderson2013-04-151-5/+8
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Introduce and use tcg_out_ext32uRichard Henderson2013-04-151-5/+10
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Introduce and use tcg_out_rlwRichard Henderson2013-04-151-52/+20
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Use TCGReg everywhereRichard Henderson2013-04-151-15/+21
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* Merge branch 'tci' of git://qemu.weilnetz.de/qemuAurelien Jarno2013-04-132-14/+16
|\ | | | | | | | | | | | | | | | | * 'tci' of git://qemu.weilnetz.de/qemu: tci: Make tcg temporaries local to tcg_qemu_tb_exec tci: Delete unused tb_ret_addr tci: Avoid code before declarations tci: Use a local variable for env tci: Use 32-bit signed offsets to loads/stores
| * tci: Make tcg temporaries local to tcg_qemu_tb_execRichard Henderson2013-04-112-7/+13
| | | | | | | | | | | | | | | | | | | | We're moving away from the temporaries stored in env. Make sure we can differentiate between temp stores and possibly bogus stores for extra call arguments. Move TCG_AREG0 and TCG_REG_CALL_STACK out of the way of the parameter passing registers. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off by: Stefan Weil <sw@weilnetz.de>
| * tci: Delete unused tb_ret_addrRichard Henderson2013-04-111-5/+1
| | | | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off by: Stefan Weil <sw@weilnetz.de>
| * tci: Use 32-bit signed offsets to loads/storesRichard Henderson2013-04-111-2/+2
| | | | | | | | | | | | | | | | Since the change to tcg_exit_req, the first insn of every TB is a load with a negative offset from env. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off by: Stefan Weil <sw@weilnetz.de>
* | tcg-s390: Fix merge error in tgen_brcondRichard Henderson2013-04-051-1/+1
| | | | | | | | | | | | | | When the TCG condition codes were re-organized last year, we failed to update all of the "old-style" tests for unsigned. Signed-off-by: Richard Henderson <rth@twiddle.net>
* | tcg-s390: Use all 20 bits of the offset in tcg_out_memRichard Henderson2013-04-051-4/+5
| | | | | | | | | | | | | | This can save one insn, if the constant has any bits in 32-63 set, but no bits in 21-31 set. It never results in more insns. Signed-off-by: Richard Henderson <rth@twiddle.net>
* | tcg-s390: Use load-address for additionRichard Henderson2013-04-051-57/+56
| | | | | | | | | | | | | | | | Since we're always in 64-bit mode, load address performs a full 64-bit add. Use that for 3-address addition, as well as for larger constant addends when we lack extended-immediates facility. Signed-off-by: Richard Henderson <rth@twiddle.net>
* | tcg-s390: Cleanup argument shuffling fixme in softmmu codeRichard Henderson2013-04-051-47/+38
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* | tcg-s390: Use risbgz for andiRichard Henderson2013-04-051-5/+53
| | | | | | | | | | | | This is immediately usable by the tlb lookup code. Signed-off-by: Richard Henderson <rth@twiddle.net>
* | tcg-s390: Remove constraint letters for andRichard Henderson2013-04-051-117/+32
| | | | | | | | | | | | | | Since we have a free temporary and can always just load the constant, we ought to do so, rather than spending the same effort constraining the const. Signed-off-by: Richard Henderson <rth@twiddle.net>
* | tcg-s390: Implement deposit opcodesRichard Henderson2013-04-052-2/+30
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* | tcg-s390: Implement movcond opcodesRichard Henderson2013-04-052-4/+41
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* | tcg-s390: Implement mulu2_i64 opcodeRichard Henderson2013-04-052-1/+6
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* | tcg-s390: Implement add2/sub2 opcodesRichard Henderson2013-04-052-4/+42
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* | tcg-s390: Remove useless preprocessor conditionsRichard Henderson2013-04-052-14/+5
| | | | | | | | | | | | | | We only support 64-bit code generation for s390x. Don't clutter the code with ifdefs that suggest otherwise. Signed-off-by: Richard Henderson <rth@twiddle.net>
* | tcg-s390: Properly allocate a stack frame.Richard Henderson2013-04-052-7/+15
| | | | | | | | | | | | | | | | Set TCG_TARGET_CALL_STACK_OFFSET properly for the abi. Allocate the standard TCG_STATIC_CALL_ARGS_SIZE. And while we're at it, allocate space for CPU_TEMP_BUF_NLONGS. Signed-off-by: Richard Henderson <rth@twiddle.net>
* | tcg-s390: Fix moviRichard Henderson2013-04-051-1/+1
|/ | | | | The code to load the high 64 bits assumed that the insn used to load the low 64 bits zero-extended. Enforce that.
* tcg/mips: Implement muls2_i32Aurelien Jarno2013-04-012-1/+7
| | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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