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* tcg/arm: fix condition in zero/sign extension functionsAurelien Jarno2010-04-251-6/+6
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: don't try to load constants using pcAurelien Jarno2010-04-191-7/+0
| | | | | | | There is statistically almost 0 chances to use this code, so remove it. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: optimize register allocation orderAurelien Jarno2010-04-191-5/+5
| | | | | | | | | The beginning of the register allocation order list on the TCG arm target matches the list of clobbered registers. This means that when an helper is called, there is almost always clobbered registers that have to be spilled. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: fix argument alignment in qemu_st64Aurelien Jarno2010-04-191-9/+10
| | | | | | | 64-bit arguments should be aligned on an even register as specified by the "Procedure Call Standard for the ARM Architecture". Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: remove useless register tests in qemu_ld/stAurelien Jarno2010-04-191-20/+10
| | | | | | | addr_reg, data_reg and data_reg2 can't be register r0 or r1 du to the constraints. Don't check if they equals these registers. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: bswap arguments in qemu_ld/st if neededAurelien Jarno2010-04-191-69/+159
| | | | | | | | | On big endian targets, data arguments of qemu_ld/st ops have to be byte swapped. Two temporary registers are needed for qemu_st to do the bswap. r0 and r1 are used in system mode, do the same in user mode, which implies reworking the constraints. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: use ext* ops in qemu_ldAurelien Jarno2010-04-191-18/+12
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: remove conditional argument for qemu_ld/stAurelien Jarno2010-04-191-51/+49
| | | | | | | | | | While it make sense to pass a conditional argument to tcg_out_*() functions as the ARM architecture allows that, it doesn't make sense for qemu_ld/st functions. These functions use comparison instructions and conditional execution already, so it is not possible to use a second level of conditional execution. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: add bswap opsAurelien Jarno2010-04-192-2/+44
| | | | | | | | | | | Add an bswap16 and bswap32 ops, either using the rev and rev16 instructions on ARMv6+ or shifts and logical operations on previous ARM versions. In both cases the result use less instructions than the pure TCG version. These ops are also needed by the qemu_ld/st functions. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: add ext16u opAurelien Jarno2010-04-192-20/+50
| | | | | | | | | | | Add an ext16u op, either using the uxth instruction on ARMv6+ or two shifts on previous ARM versions. In both cases the result use the same number or less instructions than the pure TCG version. Also move all sign extension code to separate functions, so that they can be reused in other parts of the code. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: add rotation opsAurelien Jarno2010-04-192-1/+20
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: use the blx instruction when possibleAurelien Jarno2010-04-191-4/+12
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: sxtb and sxth are available starting with ARMv6Aurelien Jarno2010-04-191-2/+2
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: add variables to define the allowed instructions setAurelien Jarno2010-04-191-39/+84
| | | | | | | Use a set of variables to define the allowed ARM instructions, depending on the __ARM_ARCH_*__ GCC defines. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: align 64-bit arguments in function callsAurelien Jarno2010-04-191-0/+1
| | | | | | As specified by the "Procedure Call Standard for the ARM Architecture". Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: replace integer values by registers enumAurelien Jarno2010-04-191-109/+124
| | | | | | | | | | The TCG ARM backends uses integer values to refer to both immediate values and register number. This makes the code difficult to read. The patch below replaces all (if I haven't miss any ;-) integer values representing register number by TCG_REG_* enum values. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: remove store signed functionsAurelien Jarno2010-04-191-62/+10
| | | | | | | Store signed functions doesn't make sense, and are not used. Remove them. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: explicitely list clobbered/reserved regsAurelien Jarno2010-04-192-5/+11
| | | | | | | | | Instead of writing very compact code, declare all registers that are clobbered or reserved one by one. This makes the code easier to read. Also declare all the 16 registers to TCG, and mark pc as reserved. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: remove SAVE_LR codeAurelien Jarno2010-04-191-43/+0
| | | | | | | | | | | | There is no need to save the LR register (r14) before a call to a subroutine. According to the "Procedure Call Standard for the ARM Architecture", it is the job of the callee to save this register. Moreover, this register is already saved in the prologue/epilogue. This patch removes the disabled SAVE_LR code, as there is no need to reenable later. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/ppc: Remove redundant comparison from brcond2malc2010-04-181-2/+1
| | | | Signed-off-by: malc <av1474@comtv.ru>
* Fix --enable-profiler compilation.Richard Henderson2010-04-171-0/+1
| | | | | | | | | There's a header file inclusion ordering problem between cpu-all.h and qemu-timer.h, such that cpu_get_real_ticks is not defined when we attempt to use it in profile_getclock. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Add missing static qualifiermalc2010-04-171-1/+1
| | | | | | Build breaks otherwise when USE_LIVENESS_ANALYSIS is not defined. Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc: Fix signed versions of brcond2malc2010-04-171-1/+2
| | | | | | Thanks to: Alexander Graff, Thomas Gleixner and Andreas Faerber. Signed-off-by: malc <av1474@comtv.ru>
* tcp/mips: Change TCG_AREG0 (fp -> s0)Stefan Weil2010-04-142-3/+4
| | | | | | | | | | | | | | | | Register fp (frame pointer) is a bad choice for compilations without optimisation, because the compiler makes heavy use of this register (so the resulting code crashes). Register s0 had been used for TCG_AREG1 in earlier releases, but was no longer used and is now free for TCG_AREG0. The resulting code works for compilations without optimisation (tested with qemu mips in qemu mips on x86 host). Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/README: improve description of bswap*Aurelien Jarno2010-04-101-4/+4
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg-hppa: Don't try to calls to non-constant addresses.Richard Henderson2010-04-081-2/+4
| | | | | | | | | | PA-RISC uses procedure descriptors. We'd need to emit a call to the millicode routine $$dyncall. However, this situation doesn't actually arise, since we always have the descriptor available at TCG code generation time. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg-hppa: Fix in/out register overlap in add2/sub2.Richard Henderson2010-04-082-14/+47
| | | | | | | | Handle the output log part overlapping the input high parts. Also, improve sub2 to handle some constants the second input low part. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg-hppa: Finish the port.Richard Henderson2010-04-082-646/+1254
| | | | | | | | | | | | | | | Delete inline functions from tcg-target.h that don't need to be there, move the others to tcg-target.c. Add 'Z', 'I', 'J' constraints for 0, signed 11-bit, and signed 5-bit respectively. Add GUEST_BASE support similar to ppc64, with the value stored in a register. Add missing registers to reg_alloc_order. Add support for 12-bit branch relocations. Add functions for synthetic operations: addi, mtctl, dep, shd, vshd, ori, andi, shifts, rotates, multiply, branches, setcond. Split out TLB reads from qemu_ld and qemu_st; fix argument loading for tlb external calls. Generate the prologue. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/ia64: fix tlb addend readAurelien Jarno2010-04-081-5/+0
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/ppc64: Fix typomalc2010-04-071-1/+1
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc: Fix typomalc2010-04-061-1/+1
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc: Implment bswap16/32malc2010-04-062-2/+77
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg/mips: use seb/seh instructions on MIPS32R2Aurelien Jarno2010-04-052-8/+41
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/mips: fix 64-bit linux-user on big endian MIPSAurelien Jarno2010-04-051-4/+4
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/ppc: Implement eqv, nand and normalc2010-04-052-3/+17
| | | | Signed-off-by: malc <av1474@comtv.ru>
* Split TLB addend and target_phys_addr_tPaul Brook2010-04-054-29/+7
| | | | | | | | | | | | | | Historically the qemu tlb "addend" field was used for both RAM and IO accesses, so needed to be able to hold both host addresses (unsigned long) and guest physical addresses (target_phys_addr_t). However since the introduction of the iotlb field it has only been used for RAM accesses. This means we can change the type of addend to unsigned long, and remove associated hacks in the big-endian TCG backends. We can also remove the host dependence from target_phys_addr_t. Signed-off-by: Paul Brook <paul@codesourcery.com>
* tcg/ppc: Fix not_i32malc2010-04-041-1/+1
| | | | | | | Thanks to Alexander Graf for bug report and a good reproducible test case. Signed-off-by: malc <av1474@comtv.ru>
* tcg/TODO: remove setcondAurelien Jarno2010-04-011-1/+1
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: initial ia64 supportAurelien Jarno2010-04-012-0/+2481
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few words about design choices: * On IA64, instructions should be grouped by bundle, and dependencies between instructions declared. A first version of this code tried to schedule instructions automatically, but was very complex and too invasive for the current common TCG code (ops not ending at instruction boundaries, code retranslation breaking already generated code, etc.) It was also not very efficient, as dependencies between TCG ops is not available. Instead the option taken by the current implementation does not try to fill the bundle by scheduling instructions, but by providing ops not available as an ia64 instruction, and by offering 22-bit constant loading for most of the instructions. With both options the bundle are filled at approximately the same level. * Up to 128 registers can be affected to a function on IA64, but TCG limits this number to 64, which is actually more than enough. The register affectation is the following: - r0: used to map a constant argument with value 0 - r1: global pointer - r2, r3: internal use - r4 to r6: not used to avoid saving them - r7: env structure - r8 to r11: free for TCG (call clobbered) - r12: stack pointer - r13: thread pointer - r14 to r31: free for TCG (call clobbered) - r32: reserved (return address) - r33: reserved (PFS) - r33 to r63: free for TCG * The IA64 architecture has only 64-bit registers and no 32-bit instructions (the only exception being cmp4). Therefore 64-bit registers and instructions are used for 32-bit ops. The adopted strategy is the same as the ABI, that is the higher 32 bits are undefined. Most ops (and, or, add, shl, etc.) can directly use the 64-bit registers, while some others have to sign-extend (sar, div, etc.) or zero-extend (shr, divu, etc.) the register first. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/mips: fix branch offset during retranslationAurelien Jarno2010-03-291-19/+30
| | | | | | | Branch offsets should only be overwritten during relocation, to support partial retranslation. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: Replace qemu_ld32u (left over from previous commit)Stefan Weil2010-03-281-1/+1
| | | | | | | | | | | | | | Commit 86feb1c860dc38e9c89e787c5210e8191800385e did not change all occurrences of INDEX_op_qemu_ld32u for tcg/arm. Please note that I could not test this patch (I have currently no arm system available). Cc: Richard Henderson <rth@twiddle.net> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg-mips: add guest base supportAurelien Jarno2010-03-272-29/+39
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/mips: implement the not_i32 op the same way as gccAurelien Jarno2010-03-271-1/+1
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg-mips: implement norAurelien Jarno2010-03-272-1/+5
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson2010-03-2611-24/+37
| | | | | | | | | | | | | | | Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands sign-extended in 64-bit registers (regardless of the "real" sign of the operand). For that, we need to be able to distinguish between a 32-bit load with a 32-bit result and a 32-bit load with a given extension to a 64-bit result. This distinction already exists for the ld* loads, but not the qemu_ld* loads. Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for 32-bit outputs. Adjust all code generators to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of NOR.Richard Henderson2010-03-2610-0/+29
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of NAND.Richard Henderson2010-03-2610-0/+29
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of EQV.Richard Henderson2010-03-2611-1/+30
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Use not_i32 to implement not_i64.Richard Henderson2010-03-261-0/+3
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Change TCGType to an enumeration.Richard Henderson2010-03-262-9/+12
| | | | | | | The TCGType name was already used consistently. Changing it to an enumeration instead of a set of defines aids debugging. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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