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* tcg: Remove unused opcodesRichard Henderson2015-02-122-14/+2
| | | | | | | | We no longer need INDEX_op_end to terminate the list, nor do we need 5 forms of nop, since we just remove the TCGOp instead. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Implement insert_op_beforeRichard Henderson2015-02-123-44/+35
| | | | | | | | Rather reserving space in the op stream for optimization, let the optimizer add ops as necessary. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Remove opcodes instead of noping them outRichard Henderson2015-02-123-11/+32
| | | | | | | | With the linked list scheme we need not leave nops in the stream that we need to process later. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Put opcodes in a linked listRichard Henderson2015-02-124-495/+415
| | | | | | | | The previous setup required ops and args to be completely sequential, and was error prone when it came to both iteration and optimization. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-121-0/+12
| | | | | | | | The method by which we count the number of ops emitted is going to change. Abstract that away into some inlines. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Reduce ifdefs in tcg-op.cRichard Henderson2015-02-121-242/+207
| | | | | | | | Almost completely eliminates the ifdefs in this file, improving confidence in the lesser used 32-bit builds. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Move some opcode generation functions out of lineRichard Henderson2015-02-124-2244/+2314
| | | | | | | | | | | Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: add separate monitor command to dump opcode countersMax Filippov2014-12-172-4/+9
| | | | | | | | | | | Currently 'info jit' outputs half of the information to monitor and the rest to qemu log. Dumping opcode counts to monitor as a part of 'info jit' command doesn't sound useful. Add new monitor command 'info opcount' that only dumps opcode counters. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
* tcg/mips: fix store softmmu slow pathAurelien Jarno2014-11-021-1/+1
| | | | | | | | | | | | Commit 9d8bf2d1 moved the softmmu slow path out of line and introduce a regression at the same time by always calling tcg_out_tlb_load with is_load=1. This makes impossible to run any significant code under qemu-system-mips*. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: qemu-stable@nongnu.org Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Always enable TCGv type checkingRichard Henderson2014-09-291-55/+34
| | | | | | | | | | | Instead of using structures, which imply some amount of overhead on certain ABIs, use pointer types. This actually reduces the size of the binaries vs a NON-debug build on ppc64 and x86_64, due to a reduction in the number of sign-extension insns. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-aarch64: Use 32-bit loads for qemu_ld_i32Richard Henderson2014-09-292-14/+18
| | | | | | | | The "old" qemu_ld opcode did not specify the size of the result, and so we had to assume full register width. With the new opcodes, we can narrow the result. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Use UMULXHI instructionRichard Henderson2014-09-292-1/+6
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Rename ADDX/SUBX insnsRichard Henderson2014-09-291-7/+7
| | | | | | | The pre-v9 ADDX/SUBX insns were renamed ADDC/SUBC for v9. Standardizing on the v9 name makes things less confusing. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Use ADDXC in setcond_i64Richard Henderson2014-09-291-0/+17
| | | | | | Similar to the ADDC tricks we use in setcond_i32. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Fix setcond_i32 uninitialized valueRichard Henderson2014-09-291-2/+5
| | | | | | We failed to swap c1 and c2 correctly for NE c2 == 0. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Use ADDXC in addsub2_i64Richard Henderson2014-09-292-5/+29
| | | | | | | On T4 and newer Sparc chips we have an add-with-carry insn that takes its input from %xcc instead of %icc. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Support addsub2_i64Richard Henderson2014-09-292-9/+67
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: dump op count into qemu logzhanghailiang2014-08-241-4/+2
| | | | | | | | | fopen() may fail and it does not check its return vaule here, it is better to dump op count to the normal log file. Signed-off-by: Li Liu <john.liuli@huawei.com> Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* tcg/ppc: Fix support for 64-bit PPC MacOSX hostsPeter Maydell2014-06-291-3/+3
| | | | | | | | | | Add back in the support for 64-bit PPC MacOSX hosts that was broken in the recent merge of the 32-bit and 64-bit TCG backends. Reported-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Tested-by: Andreas Färber <andreas.faerber@web.de>
* tcg/ppc: Fix failure in tcg_out_mem_longRichard Henderson2014-06-271-1/+4
| | | | | | | | | | With rt != r0 on loads, we use rt for scratch. If we need an index register different from base, we can't use rt, but r0 is usable. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1403843160-30332-1-git-send-email-rth@twiddle.net Tested-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* tcg: mark tcg_out* and tcg_patch* with attribute 'unused'Peter Maydell2014-06-241-8/+12
| | | | | | | | | The tcg_out* and tcg_patch* functions are utility routines that may or may not be used by a particular backend; mark them with the 'unused' attribute to suppress spurious warnings if they aren't used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* Fix new typos (found by codespell)Stefan Weil2014-06-241-2/+2
| | | | | | | | | | | | * accomodate -> accommodate * aquiring -> acquiring * beacuse -> because * loosing -> losing * prefering -> preferring * threshhold -> threshold Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* tcg-ppc: Use the return address as a base pointerRichard Henderson2014-06-231-12/+93
| | | | | | | | | This can significantly reduce code size for generation of (some) 64-bit constants. With the side effect that we know for a fact that exit_tb can use the register to good effect. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc: Merge cache-utils into the backendRichard Henderson2014-06-233-1/+98
| | | | | | | | | As a "utility", it only supported ppc, and in a way that other tcg backends provided directly in tcg-target.h. Removing this disparity is easier now that the two ppc backends are merged. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc: Rename the tcg/ppc64 backendRichard Henderson2014-06-232-0/+0
| | | | | | | | The other tcg backends that support 32- and 64-bit modes use the 32-bit name for the port. Follow suit. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc: Remove the backendRichard Henderson2014-06-232-2042/+0
| | | | | | | Vectoring the 32-bit build to the ppc64 directory. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Merge ppc32 shiftsRichard Henderson2014-06-231-8/+32
| | | | | Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Support mulsh_i32Richard Henderson2014-06-232-1/+6
| | | | | Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Merge ppc32 register usageRichard Henderson2014-06-231-22/+39
| | | | | | | Good enough to run some instructions before things go awry. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Merge ppc32 qemu_ld/stRichard Henderson2014-06-231-84/+209
| | | | | Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Merge ppc32 brcond2, setcond2, muluhRichard Henderson2014-06-232-2/+96
| | | | | | | | Now passes tcg_add_target_add_op_defs assertions, but not complete enough to function. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Begin merging ppc32 with ppc64Richard Henderson2014-06-232-43/+81
| | | | | | | | Just enough to compile, assuming you edit config-host.mak manually. It will still abort at runtime, due to missing brcond2, setcond2, mulu2. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Fix sub2 implementationRichard Henderson2014-06-231-7/+7
| | | | | | | All sorts of confusion on argument ordering. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Merge 32-bit ABIs into the prologue / frame codeRichard Henderson2014-06-231-7/+32
| | | | | Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Adjust tcg_out_call for ELFv2Ulrich Weigand2014-06-231-0/+17
| | | | | | | | | | | | | | The new ELFv2 ABI, used by default on powerpc64le-linux hosts, introduced some changes that are incompatible with code currently generated by the ppc64 TGC target. In particular, we no longer use function descriptors. This patch adds support for the ELFv2 ABI in the ppc64 TGC function call and function prologue sequences. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Ulrich Weigand <ulrich.weigand@de.ibm.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Support the ppc64 elfv2 ABIRichard Henderson2014-06-231-0/+4
| | | | | Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Use the correct test in tcg_out_callRichard Henderson2014-06-231-3/+3
| | | | | | | The correct test uses the _CALL_AIX macro, not a host-specific macro. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Better parameterize the stack frameRichard Henderson2014-06-231-28/+36
| | | | | | | In preparation for supporting other ABIs. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Fix TCG_TARGET_CALL_STACK_OFFSETRichard Henderson2014-06-231-1/+1
| | | | | | | | | The calling convention reserves space for the 8 register parameters on the stack, so using only 6*8=48 as the offset was wrong. We never saw this bug because we don't have any helpers with more than 5 parameters. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Move call macros out of tcg-target.hRichard Henderson2014-06-232-6/+5
| | | | | | | | These values are private to tcg.c; we don't need to expose this nonsense to the translators. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Make TCG_AREG0 and TCG_REG_CALL_STACK enum constantsRichard Henderson2014-06-231-35/+11
| | | | | Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Use tcg_out_{ld,st,cmp} internallyRichard Henderson2014-06-231-19/+14
| | | | | | | | Rather than using tcg_out32 and opcodes directly. This allows us to remove LD_ADDR and CMP_L macros. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Relax register restrictions in tcg_out_mem_longRichard Henderson2014-06-231-5/+7
| | | | | | | | In order to be able to use tcg_out_ld/st sensibly with scratch registers, assert only when we'd incorrectly clobber a scratch. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Move functions aroundRichard Henderson2014-06-231-361/+361
| | | | | | | | Code movement only. This will allow us to make use of the other tcg_out_* functions in tidying their implementations. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Avoid some hard-codings of TCG_TYPE_I64Richard Henderson2014-06-231-10/+13
| | | | | | | Using more appropriate _PTR or _REG where possible. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc: Use uintptr_t in ppc_tb_set_jmp_targetRichard Henderson2014-06-231-1/+1
| | | | | Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/optimize: Don't special case TCG_OPF_CALL_CLOBBERRichard Henderson2014-06-181-5/+4
| | | | | | | With the "old" ldst ops we didn't know the real width of the result of the load, but with the "new" ldst ops we do. Signed-off-by: Richard Henderson <rth@twiddle.net>
* Merge remote-tracking branch 'remotes/bonzini/softmmu-smap' into stagingPeter Maydell2014-06-051-13/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * remotes/bonzini/softmmu-smap: (33 commits) target-i386: cleanup x86_cpu_get_phys_page_debug target-i386: fix protection bits in the TLB for SMEP target-i386: support long addresses for 4MB pages (PSE-36) target-i386: raise page fault for reserved bits in large pages target-i386: unify reserved bits and NX bit check target-i386: simplify pte/vaddr calculation target-i386: raise page fault for reserved physical address bits target-i386: test reserved PS bit on PML4Es target-i386: set correct error code for reserved bit access target-i386: introduce support for 1 GB pages target-i386: introduce do_check_protect label target-i386: tweak handling of PG_NX_MASK target-i386: commonize checks for PAE and non-PAE target-i386: commonize checks for 4MB and 4KB pages target-i386: commonize checks for 2MB and 4KB pages target-i386: fix coding standards in x86_cpu_handle_mmu_fault target-i386: simplify SMAP handling in MMU_KSMAP_IDX target-i386: fix kernel accesses with SMAP and CPL = 3 target-i386: move check_io helpers to seg_helper.c target-i386: rename KSMAP to KNOSMAP ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * softmmu: move all load/store functions to cpu_ldst.hPaolo Bonzini2014-06-051-13/+0
| | | | | | | | | | | | | | | | Unify pieces of cpu-all.h, exec-all.h, softmmu_exec.h and tcg/tcg.h into a single new header file with all helpers. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | TCG: Fix tcg_gen_extr_i64_tl for 32bitAlexander Graf2014-06-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | We expose a generic helper "tcg_gen_extr_i64_tl" for 64bit targets, but the same function for 32bit targets is a misnomer and refers to an invalid function name. Fix up the definition to point to the correct internal helper names instead. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
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