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* tcg-sparc: Implement brcond2.Richard Henderson2009-12-211-14/+69
| | | | | | | | | Split out tcg_out_cmp and properly handle immediate arguments. Fix constraints on brcond to match what SUBCC accepts. Add tcg_out_brcond2_i32 for 32-bit host. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation.Richard Henderson2009-12-211-16/+16
| | | | | | | | | | The test TCG_TARGET_REG_BITS==64 is exactly the feature that we are checking for, whereas something involving __sparc_v9__ or __sparc_v8plus__ should be reserved for something ISA related, as with SMULX. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg-sparc: Improve tcg_out_movi for sparc64.Richard Henderson2009-12-211-12/+15
| | | | | | | | | Generate sign-extended 32-bit constants with SETHI+XOR. Otherwise tidy the routine to avoid the need for conditional compilation and code duplication with movi_imm32. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg-sparc: Fix imm13 check in movi.Richard Henderson2009-12-211-1/+1
| | | | | | | We were unnecessarily restricting imm13 constants to 12 bits. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg/ppc64: Fix loading of 32bit constantsmalc2009-12-151-1/+2
| | | | Signed-off-by: malc <av1474@comtv.ru>
* TCG: Mac OS X support for ppc64 targetAndreas Faerber2009-12-061-14/+41
| | | | | | | | | | | | | | | | | Darwin/ppc64 does not use function descriptors, adapt prologue and tcg_out_call accordingly. GPR2 is available for general use, so let's use it. http://developer.apple.com/mac/library/documentation/DeveloperTools/Conceptual/LowLevelABI/110-64-bit_PowerPC_Function_Calling_Conventions/64bitPowerPC.html v2: - Don't mark reserved GPR13 as callee-save. - Move tcg_out_b up. - Fix unused variable warning in prologue. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Cc: malc <av1474@comtv.ru> Signed-off-by: malc <av1474@comtv.ru>
* S/390 fake TCG implementationAlexander Graf2009-12-052-0/+174
| | | | | | | | | | | | Qemu won't let us run a KVM target without having host TCG support. Well, for now we don't have any so let's implement a fake target that only stubs out everything. I tried to keep the patch as close to Uli's source as possible, so whenever he feels like it he can easily diff his version against this one. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: initial mips supportAurelien Jarno2009-12-012-0/+1446
| | | | | | | | | | | | | | | | Based on a patch from Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org> A few words about design choices: * Two registers, at and t0, are reserved for TCG internal use. They are useful for bswap and 64-bit ops. * Most ops supports a constant argument with value 0, which is actually mapped to the zero register. * While the at register is available for constant loading, ops only support a limited range of constants. TCG does a better job doing the register allocation and constant loading by itself. There are plenty of registers available anyway. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: fix tcg_regset_{set,reset}_reg with more than 32 registersAurelien Jarno2009-11-241-2/+2
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/ppc64,x86_64: fix constraints of op_qemu_st64Aurelien Jarno2009-11-242-2/+2
| | | | | | This op only takes two arguments, not two. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/i386: remove duplicate sar opcodeMagnus Damm2009-11-141-1/+0
| | | | | Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: improve output logAurelien Jarno2009-10-071-1/+1
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: allocate s->op_dead_iargs dynamicallyAurelien Jarno2009-10-041-2/+1
| | | | | | | Similarly to what is already done in tcg_liveness_analysis() when USE_LIVENESS_ANALYSIS is not set. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: remove dead codeAurelien Jarno2009-10-041-2/+0
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/i386: add support for ext{8,16}u_i32 TCG opsAurelien Jarno2009-10-042-0/+10
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/x86_64: add support for ext{8,16,32}u_i{32,64} TCG opsAurelien Jarno2009-10-042-0/+26
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: add ext{8,16,32}u_i{32,64} TCG opsAurelien Jarno2009-10-042-3/+36
| | | | | | | | | | | | | | | | | | | | | Currently zero extensions ops are implemented by a and op with a constant. This is then catched in some backend, and replaced by a zero extension instruction. While this works well on RISC machines, this adds a useless register move on non-RISC machines. Example on x86: ext16u_i32 r1, r2 is translated into mov %eax,%ebx movzwl %bx, %ebx while the optimized version should be: movzwl %ax, %ebx This patch adds ext{8,16,32}u_i{32,64} TCG ops that can be implemented in the backends to avoid emitting useless register moves. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Revert part of 6692b043198d58a12317009edb98654c6839f043Aurelien Jarno2009-09-301-8/+4
| | | | | | Committed by accident. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* TCG: fix DEF2 macroAurelien Jarno2009-09-301-5/+9
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/i386: generates dec/inc instead of sub/add when possibleAurelien Jarno2009-09-271-9/+15
| | | | | | | We must take care that dec/inc do not compute CF, which is needed by add2/sub2. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/i386: optimize and $0xff(ff), regAurelien Jarno2009-09-271-0/+6
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/x86_64: generated dec/inc instead of sub/add when possibleAurelien Jarno2009-09-271-2/+14
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/ppc: always use tcg_out_callmalc2009-09-271-20/+10
| | | | Signed-off-by: malc <av1474@comtv.ru>
* ARM back-end: Use sxt[bh] instructions for ext{8, 6}sLaurent Desnogues2009-09-261-0/+10
| | | | | | | This patch uses sxtb for ext8s_i32 and sxth for ext16s_i32 in ARM back-end. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Suppress some variants of English in commentsStefan Weil2009-09-252-4/+4
| | | | | | | Replace surpress, supress by suppress. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Compile TCG runtime library only onceBlue Swirl2009-09-203-77/+14
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: fix size of local variables in tcg_gen_bswap64_i64Stefan Weil2009-09-161-5/+4
| | | | | | | t0, t1 must be 64 bit values, not 32 bit. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* X86_64: Use proper jumps/calls when displacement exceeds +-2Gmalc2009-09-111-12/+19
| | | | Signed-off-by: malc <av1474@comtv.ru>
* When targeting PPU use rlwinm instead of andi. if possiblemalc2009-09-061-8/+54
| | | | | | andi. is microcoded and slow there. Signed-off-by: malc <av1474@comtv.ru>
* ARM back-end: Fix encode_immLaurent Desnogues2009-08-251-0/+2
| | | | | | | | | the encode_imm function in tcg/arm/tcg-target.c lacks shift declaration. Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* ARM back-end: Handle all possible immediates for ALU opsLaurent Desnogues2009-08-221-5/+32
| | | | | | | | | | this patch handles all possible constants for immediate operand of ALU ops. I'm not very satisfied by the implementation. Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* ARM back-end: Add TCG notLaurent Desnogues2009-08-222-0/+6
| | | | | | | | | | | this patch: - implements TCG not. Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIANJuan Quintela2009-07-271-1/+1
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* rename DEBUG_TCG to CONFIG_DEBUG_TCGJuan Quintela2009-07-272-2/+2
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* change HOST_SOLARIS to CONFIG_SOLARIS{_VERSION}Juan Quintela2009-07-271-1/+1
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Fix CONFIG_PROFILERBlue Swirl2009-07-211-5/+3
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Fix rbase initializationmalc2009-07-201-1/+1
| | | | Signed-off-by: malc <av1474@comtv.ru>
* this patch improves the ARM back-end in the following way:Laurent Desnogues2009-07-182-7/+37
| | | | | | | | | | - use movw/movt to load immediate values for ARMv7-A - implement add/sub/and/or/xor with immediate (only 8-bit) Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* tcg: Fix tcg_gen_rotr_i64Aurelien Jarno2009-07-181-1/+1
| | | | | Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* PPC 32/64 GUEST_BASE supportmalc2009-07-184-41/+127
| | | | Signed-off-by: malc <av1474@comtv.ru>
* Fix LHZX opcode valuemalc2009-07-182-2/+2
| | | | Signed-off-by: malc <av1474@comtv.ru>
* Userspace guest address offsettingJuan Quintela2009-07-171-1/+1
| | | | | | Fix type in i386 tcg. Signed-off-by: Juan Quintela <quintela@redhat.com>
* Userspace guest address offsettingPaul Brook2009-07-177-33/+103
| | | | | | | | | | Re-implement GUEST_BASE support. Offset guest ddress space by default if the guest binary contains regions below the host mmap_min_addr. Implement support for i386, x86-64 and arm hosts. Signed-off-by: Riku Voipio <riku.voipio@iki.fi> Signed-off-by: Paul Brook <paul@codesourcery.com>
* ARM host fixesPaul Brook2009-07-172-4/+4
| | | | | | Minor TCG cleanups and warning fixes for ARM hosts. Signed-off-by: Paul Brook <paul@codesourcery.com>
* Include assert.h from qemu-common.hPaul Brook2009-05-131-1/+0
| | | | | | | Include assert.h from qemu-common.h and remove other direct uses. cpu-all.h still need to include it because of the dyngen-exec.h hacks Signed-off-by: Paul Brook <paul@codesourcery.com>
* tcg: make sure NDEBUG is defined before including <assert.h>aurel322009-04-161-6/+7
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7122 c046a42c-6fe2-441c-8c8c-71466251a162
* Add a --enable-debug-tcg option to configureaurel322009-04-132-4/+9
| | | | | | | | | | | | | This patch allows DEBUG_TCGV to be defined (and also prevents NDEBUG from being defined) when passing an option to the configure script. This should help to prevent any accidental changes that enable DEBUG_TCGV in tcg/tcg.h from being committed in future, and may help to encourage testing with DEBUG_TCGV enabled. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7105 c046a42c-6fe2-441c-8c8c-71466251a162
* Remove reserved registers from tcg_target_reg_alloc_ordermalc2009-04-111-4/+0
| | | | | | Noticed by Andreas Faerber git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7082 c046a42c-6fe2-441c-8c8c-71466251a162
* Whack [LS]MWmalc2009-04-112-6/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
* Remove reserved registers from tcg_target_reg_alloc_ordermalc2009-04-111-3/+0
| | | | | | Noticed by Andreas Faerber git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7080 c046a42c-6fe2-441c-8c8c-71466251a162
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