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* tcg/optimize: fix setcond2 optimizationAurelien Jarno2013-05-091-0/+1
| | | | | | | | | | When setcond2 is rewritten into setcond, the state of the destination temp should be reset, so that a copy of the previous value is not used instead of the result. Reported-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg-arm: Use movi32 in exit_tbRichard Henderson2013-05-031-9/+7
| | | | | | | | Avoid the mini constant pool for armv7, and avoid replicating the test for pre-v7. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg-arm: Fix 64-bit tlb load for pre-v6Richard Henderson2013-05-031-1/+1
| | | | | | | | Found by inspection, since the effect of the bug was simply to send all memory ops through the slow path. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg-arm: Remove long jump from tcg_out_goto_labelRichard Henderson2013-04-271-6/+1
| | | | | | Branches within a TB will always be within 16MB. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Convert to CONFIG_QEMU_LDST_OPTIMIZATIONRichard Henderson2013-04-271-107/+202
| | | | | | | | Move the slow path out of line, as the TODO's mention. This allows the fast path to be unconditional, which can speed up the fast path as well, depending on the core. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Use movi32 + blx for calls on v7Richard Henderson2013-04-271-0/+3
| | | | | | | | | Work better with branch predition when we have movw+movt, as the size of the code is the same. Perhaps re-evaluate when we have a proper constant pool. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Delete the 'S' constraintRichard Henderson2013-04-271-4/+2
| | | | | | After the previous patch, 's' and 'S' are the same. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Improve scheduling of tcg_out_tlb_readRichard Henderson2013-04-271-53/+57
| | | | | | | | The schedule was fully serial, with no possibility for dual issue. The old schedule had a minimal issue of 7 cycles; the new schedule has a minimal issue of 5 cycles. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Split out tcg_out_tlb_readRichard Henderson2013-04-271-99/+70
| | | | | | | Share code between qemu_ld and qemu_st to process the tlb. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Cleanup most primitive load store subroutinesRichard Henderson2013-04-271-124/+111
| | | | | | | Use even more primitive helper functions to avoid lots of duplicated code. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Cleanup multiply subroutinesRichard Henderson2013-04-271-40/+45
| | | | | | | | | Make the code more readable by only having one copy of the magic numbers, swapping registers as needed prior to that. Speed the compiler by not applying the rd == rn avoidance for v6 or later. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Use R12 for the tcg temporaryRichard Henderson2013-04-271-1/+1
| | | | | | | | R12 is call clobbered, while R8 is call saved. This change gives tcg one more call saved register for real data. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Use TCG_REG_TMP name for the tcg temporaryRichard Henderson2013-04-271-58/+60
| | | | | | | Don't hard-code R8. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Implement division instructionsRichard Henderson2013-04-272-1/+42
| | | | | | | An armv7 extension implements division, present on Cortex A15. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Implement deposit for armv7Richard Henderson2013-04-272-4/+42
| | | | | | We have BFI and BFC available for implementing it. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Improve constant generationRichard Henderson2013-04-271-23/+44
| | | | | | | | | | | | | | | | Try fully rotated arguments to mov and mvn before trying movt or full decomposition. Begin decomposition with mvn when it looks like it'll help. Examples include -: mov r9, #0x00000fa0 -: orr r9, r9, #0x000ee000 -: orr r9, r9, #0x0ff00000 -: orr r9, r9, #0xf0000000 +: mvn r9, #0x0000005f +: eor r9, r9, #0x00011000 Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Handle constant arguments to add2/sub2Richard Henderson2013-04-271-48/+58
| | | | | | | | | We get to re-use the _rIN and _rIK subroutines to handle the various combinations of add vs sub. Fold the << 21 into the opcode enum values so that we can explicitly add TO_CPSR as desired. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Use tcg_out_dat_rIN for comparesRichard Henderson2013-04-271-20/+20
| | | | | | | This allows us to emit CMN instructions. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Allow constant first argument to subRichard Henderson2013-04-271-3/+12
| | | | | | | This allows the generation of RSB instructions. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Handle negated constant arguments to and/subRichard Henderson2013-04-271-6/+35
| | | | | | | | This greatly improves code generation for addition of small negative constants. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Use bic to implement and with constantRichard Henderson2013-04-272-14/+44
| | | | | | | | This greatly improves the code we can produce for deposit without armv7 support. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Log the contents of the prologue with -d out_asmRichard Henderson2013-04-271-0/+10
| | | | | | | | | | This makes it easier to verify changes to the code generating the prologue. [Aurelien: change the format from %i to %zu] Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Fix local stack frameRichard Henderson2013-04-271-74/+47
| | | | | | | | | | | | We were not allocating TCG_STATIC_CALL_ARGS_SIZE, so this meant that any helper with more than 4 arguments would clobber the saved regs. Realizing that we're supposed to have this memory pre-allocated means we can clean up the tcg_out_arg functions, which were trying to do more stack allocation. Allocate stack memory for the TCG temporaries while we're at it. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: fix deposit_i64 op on 32-bit targetsAurelien Jarno2013-04-271-1/+1
| | | | | | | | | | | | | | On 32-bit TCG targets, when emulating deposit_i64 with a mov_i32 + deposit_i32, care should be taken to not overwrite the low part of the second argument before the deposit when it is the same the destination. This fixes the shld instruction in qemu-system-x86_64, which in turns fixes booting "system rescue CD version 2.8.0" on this target. Reported-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg-ppc64: Handle deposit of zeroRichard Henderson2013-04-151-6/+16
| | | | | | | | | | The TCG optimizer does great work when inserting constants, being able to fold the open-coded deposit expansion to just an AND or an OR. Avoid a bit the regression caused by having the deposit opcode by expanding deposit of zero as an AND. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Implement mulu2/muls2_i64Richard Henderson2013-04-152-2/+29
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Implement add2/sub2_i64Richard Henderson2013-04-152-2/+58
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Use getauxval for ISA detectionRichard Henderson2013-04-151-0/+14
| | | | | | | | Glibc 2.16 includes an easy way to get feature bits previously buried in /proc or the program startup auxiliary vector. Use it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Implement movcondRichard Henderson2013-04-152-2/+61
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Use ISEL for setcondRichard Henderson2013-04-151-62/+119
| | | | | | | | There are a few simple special cases that should be handled first. Break these out to subroutines to avoid code duplication. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Use MFOCRF instead of MFCRRichard Henderson2013-04-151-4/+8
| | | | | | | | | It takes half the cycles to read one CR register instead of all 8. This is a backward compatible addition to the ISA, so chips prior to Power 2.00 spec will simply continue to read the entire CR register. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Cleanup i32 constants to tcg_out_cmpRichard Henderson2013-04-151-0/+5
| | | | | | | | Nothing else in the call chain ensures that these constants don't have garbage in the high bits. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Use TCGType throughout comparesRichard Henderson2013-04-151-19/+19
| | | | | | | | | | The optimization/bug being fixed is that tcg_out_cmp was not applying the right type to loading a constant, in the case it can't be implemented directly. Rather than recomputing the TCGType enum from the arch64 bool, pass around the original TCGType throughout. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Use I constraint for mulRichard Henderson2013-04-151-12/+12
| | | | | | | | | The mul_i32 pattern was loading non-16-bit constants into a register, when we can get the middle-end to do that for us. The mul_i64 pattern was not considering that MULLI takes 64-bit inputs. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Implement depositRichard Henderson2013-04-152-2/+14
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Handle constant inputs for some compound logicalsRichard Henderson2013-04-151-10/+34
| | | | | | | | Since we have special code to handle and/or/xor with a constant, apply the same to andc/orc/eqv with a constant. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Implement compound logicalsRichard Henderson2013-04-152-10/+44
| | | | | | | Mostly copied from the ppc32 port. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Implement bswap64Richard Henderson2013-04-152-1/+36
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Implement bswap16 and bswap32Richard Henderson2013-04-152-4/+47
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Implement rotatesRichard Henderson2013-04-152-2/+41
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Streamline qemu_ld/st insn selectionRichard Henderson2013-04-151-110/+56
| | | | | | | | Using a table to look up insns of the right width and sign. Include support for the Power 2.06 LDBRX and STDBRX insns. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Use automatic implementation of ext32u_i64Richard Henderson2013-04-152-8/+3
| | | | | | | The enhancements to and immediate obviate this. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Improve and_i64 with constantRichard Henderson2013-04-151-14/+50
| | | | | | | Use RLDICL and RLDICR. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Improve and_i32 with constantRichard Henderson2013-04-152-3/+53
| | | | | | | Use RLWINM Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Tidy or and xor patterns.Richard Henderson2013-04-151-24/+31
| | | | | | | Handle constants in common code; we'll want to reuse that later. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Allow constant first argument to subRichard Henderson2013-04-151-4/+17
| | | | | | | Using SUBFIC for 16-bit signed constants. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Improve constant add and sub ops.Richard Henderson2013-04-151-44/+64
| | | | | | | | | Improve constant addition -- previously we'd emit useless addi with 0. Use new constraints to force the driver to pull full 64-bit constants into a register. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Rearrange integer constant constraintsRichard Henderson2013-04-151-10/+33
| | | | | | | | We'll need a zero, and Z makes more sense for that. Make sure we have a full compliment of signed and unsigned 16 and 32-bit tests. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Cleanup tcg_out_moviRichard Henderson2013-04-151-24/+17
| | | | | | | | | | | The test for using movi32 was sub-optimal for TCG_TYPE_I32, comparing a signed 32-bit quantity against an unsigned 32-bit quantity. When possible, use addi+oris for 32-bit unsigned constants. Otherwise, standardize on addi+oris+ori instead of addis+ori+rldicl. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc64: Fix setcond_i32Richard Henderson2013-04-151-0/+6
| | | | | | | We weren't ignoring the high 32 bits during a NE comparison. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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