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* | tcg-sparc: Implement movcond.Richard Henderson2012-10-132-9/+38
| | | | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | tcg-sparc: Fix brcond2Richard Henderson2012-10-131-16/+7
|/ | | | | | | Much the same problem as recently fixed for hppa. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Remove redundant pointer from TCGContextStefan Weil2012-10-072-3/+1
| | | | | | | | | | The pointer entry 'temps' always refers to the array entry 'static_temps'. Removing the pointer and renaming 'static_temps' to 'temps' reduces the size of TCGContext (4 or 8 byte) and allows better code generation. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Merge branch 'trivial-patches' of git://github.com/stefanha/qemuAurelien Jarno2012-10-061-12/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'trivial-patches' of git://github.com/stefanha/qemu: versatilepb: Use symbolic indices for ARM PIC qdev: kill bogus comment qemu-barrier: Fix compiler version check for future gcc versions hw: Add missing 'static' attribute for QEMUMachine cleanup useless return sentence qemu-sockets: Fix compiler warning (regression for MinGW) vnc: Fix spelling (hellmen -> hellman) in comment slirp: Fix spelling in comment (enought -> enough, insure -> ensure) tcg/arm: Use tcg_out_mov_reg rather than inline equivalent code cpu: Add missing 'static' attribute to qemu_global_mutex configure: Support empty target list (--target-list=) hw: Fix return value check for bdrv_read, bdrv_write
| * tcg/arm: Use tcg_out_mov_reg rather than inline equivalent codePeter Maydell2012-10-051-12/+3
| | | | | | | | | | | | | | | | | | Use the recently introduced tcg_out_mov_reg() function rather than the equivalent inline code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Hajnoczi <stefanha@gmail.com>
* | tcg: Add tcg_high_condRichard Henderson2012-10-062-15/+19
| | | | | | | | | | | | | | | | | | The table that was recently added for hppa is generally usable. And with the renumbering of the TCG_COND constants it's not too difficult to compute rather than have a table. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | tcg: Add TCG_COND_NEVER, TCG_COND_ALWAYSRichard Henderson2012-10-0611-41/+102
| | | | | | | | | | | | | | | | | | | | There are several cases that can be handled easier inside both translators and code generators if we have out-of-band values for conditions. It's easy enough to handle ALWAYS and NEVER in the natural way inside the tcg middle-end. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | tcg: Add is_unsigned_condRichard Henderson2012-10-062-1/+6
| | | | | | | | | | | | | | | | Before we rearrange the TCG_COND enumeration, add a predicate for the (single) use of comparisons vs TCGCond. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | tcg: remove obsolete jmp opAurelien Jarno2012-10-0612-70/+1
|/ | | | | | | | | | | | | The TCG jmp operation doesn't really make sense in the QEMU context, it is unused, it is not implemented by some targets, and it is wrongly implemented by some others. This patch simply removes it. Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Stefan Weil<sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tci: Fix for AREG0 free modeStefan Weil2012-09-271-5/+5
| | | | | | | | | | | | Support for helper functions with 5 arguments was missing in the code generator and in the interpreter. There is no need to pass the constant TCG_AREG0 from the code generator to the interpreter. Remove that code for the INDEX_op_qemu_st* opcodes. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/i386: fix build with -march < i686Aurelien Jarno2012-09-261-0/+2
| | | | | | | | | | The movcond_i32 op has to be protected with TCG_TARGET_HAS_movcond_i32 to fix the build with -march < i686. Thanks to Richard Henderson for the hint. Reported-by: Alex Barcelo <abarcelo@ac.upc.edu> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Streamline movcond_i64 using movcond_i32Richard Henderson2012-09-261-7/+15
| | | | | | | | | When movcond_i32 is available we can further reduce the generated op count from 12 to 6, and the generated code size on i686 from 88 to 74 bytes. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Streamline movcond_i64 using 32-bit arithmeticRichard Henderson2012-09-261-0/+20
| | | | | | | | | Avoiding 64-bit arithmetic (outside of the compare) reduces the generated op count from 15 to 12, and the generated code size on i686 from 105 to 88 bytes. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Sanity check goto_tb inputRichard Henderson2012-09-263-2/+14
| | | | | | | | | | Checking that we don't try for idx != [01] is trivial. Checking that we don't issue more than one of any index requires a tad more data and some ifdefs protecting that new variable. Signed-off-by: Richard Henderson <rth@twiddle.net> Cc: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Sanity check deposit inputsRichard Henderson2012-09-261-0/+8
| | | | | | | | Given these are constants, checking once here means everything after can assume they're correct. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Add tcg_debug_assertRichard Henderson2012-09-261-0/+9
| | | | | | | | | | | | Like the C assert macro, except only enabled for CONFIG_DEBUG_TCG, and without having to set _NDEBUG and disable all other asserts at the same time. The use of __builtin_unreachable (when available) gives the compiler the same information, which may (or may not) help it optimize better. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Implement concat*_i64 with deposit_i64Richard Henderson2012-09-261-30/+30
| | | | | | | | | | | For tcg_gen_concat_i32_i64 we only use deposit if the host supports it. For tcg_gen_concat32_i64 even if the host does not, as we get identical code before and after. Note that this relies on the ANDI -> EXTU patch for the identity claim. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Emit XORI as NOT for appropriate constantsRichard Henderson2012-09-261-4/+15
| | | | | | | | Note that xori_i64 failed to perform even the minimal optimizations promised by the README. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Optimize initial inputs for ori_i64Richard Henderson2012-09-261-6/+13
| | | | | | | Copy the same optimizations from ori_i32. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Emit ANDI as EXTU for appropriate constantsRichard Henderson2012-09-261-11/+56
| | | | | | | | Note that andi_i64 failed to perform even the minimal optimizations promised by the README. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Adjust descriptions of *cond opcodesRichard Henderson2012-09-261-5/+5
| | | | | | | | | | The README file documented the operand ordering of the tcg_gen_* functions. Since we're documenting opcodes here, use the true operand ordering. Signed-off-by: Richard Henderson <rth@twiddle.net> Cc: malc <av1474@comtv.ru> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/mips: fix MIPS32(R2) detectionAurelien Jarno2012-09-262-9/+9
| | | | | | | | Fix the MIPS32(R2) cpu detection so that it also works with -march=octeon. Thanks to Andrew Pinski for the hint. Cc: Andrew Pinski <apinski@cavium.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Merge branch 'tcg-sparc' of git://repo.or.cz/qemu/rthBlue Swirl2012-09-223-528/+478
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'tcg-sparc' of git://repo.or.cz/qemu/rth: tcg-sparc: Preserve branch destinations during retranslation tcg-sparc: Fix and enable direct TB chaining. tcg-sparc: Add %g/%o registers to alloc_order tcg-sparc: Use defines for temporaries. tcg-sparc: Mask shift immediates to avoid illegal insns. tcg-sparc: Clean up cruft stemming from attempts to use global registers. tcg-sparc: Change AREG0 in generated code to %i0. tcg-sparc: Support GUEST_BASE. tcg-sparc: Fix qemu_ld/st to handle 32-bit host. tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode. tcg-sparc: Don't MAP_FIXED on top of the program tcg-sparc: Fix ADDX opcode. tcg-sparc: Hack in qemu_ld/st64 for 32-bit. linux-user: Use memcpy in get_user/put_user.
| * tcg-sparc: Preserve branch destinations during retranslationRichard Henderson2012-09-211-8/+11
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg-sparc: Fix and enable direct TB chaining.Richard Henderson2012-09-211-3/+18
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg-sparc: Add %g/%o registers to alloc_orderRichard Henderson2012-09-211-0/+13
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg-sparc: Use defines for temporaries.Richard Henderson2012-09-211-56/+59
| | | | | | | | | | | | And change from %i4/%i5 to %g1/%o7 to remove a v8plus fixme. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg-sparc: Mask shift immediates to avoid illegal insns.Richard Henderson2012-09-211-6/+12
| | | | | | | | | | | | | | | | The xtensa-test image generates a sra_i32 with count 0x40. Whether this is accident of tcg constant propagation or originating directly from the instruction stream is immaterial. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg-sparc: Clean up cruft stemming from attempts to use global registers.Richard Henderson2012-09-212-47/+26
| | | | | | | | | | | | | | Don't use -ffixed-gN. Don't link statically. Don't save/restore AREG0 around calls. Don't allocate space on the stack for AREG0 save. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg-sparc: Change AREG0 in generated code to %i0.Richard Henderson2012-09-212-8/+3
| | | | | | | | | | | | | | We can now move the TCG variable from %g[56] to a call-preserved windowed register. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg-sparc: Support GUEST_BASE.Richard Henderson2012-09-212-3/+25
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg-sparc: Fix qemu_ld/st to handle 32-bit host.Richard Henderson2012-09-211-429/+348
| | | | | | | | | | | | | | | | At the same time, split out the tlb load logic to a new function. Fixes the cases of two data registers and two address registers. Fixes the signature of, and adds missing, qemu_ld/st opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode.Richard Henderson2012-09-213-19/+11
| | | | | | | | | | | | | | | | | | Current code doesn't actually work in 32-bit mode at all. Since no one really noticed, drop the complication of v7 and v8 cpus. Eliminate the --sparc_cpu configure option and standardize macro testing on TCG_TARGET_REG_BITS / HOST_LONG_BITS Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg-sparc: Fix ADDX opcode.Richard Henderson2012-09-211-1/+1
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg-sparc: Hack in qemu_ld/st64 for 32-bit.Richard Henderson2012-09-211-0/+3
| | | | | | | | | | | | Not actually implemented, but at least we avoid the tcg assert at startup. Signed-off-by: Richard Henderson <rth@twiddle.net>
* | Revert "tcg/mips"Aurelien Jarno2012-09-221-2/+2
| | | | | | | | | | | | | | | | This reverts commit ad49d1f75115663731bfe06dec61eed6775526ad. This commit was not supposed to be pushed. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | tcg/ppc32: Implement movcond32malc2012-09-222-1/+76
| | | | | | | | | | | | Thanks to Richard Henderson Signed-off-by: malc <av1474@comtv.ru>
* | tcg/mipsAurelien Jarno2012-09-221-2/+2
| |
* | tcg: Remove tcg_target_get_call_iarg_regs_countStefan Weil2012-09-2211-61/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The TCG targets no longer need individual implementations. Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9, 'flags' is no longer used in tcg_target_get_call_iarg_regs_count. The remaining tcg_target_get_call_iarg_regs_count is trivial and only called once. Therefore the patch eliminates it completely. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | tcg/i386: Remove unused registers from tcg_target_call_iarg_regsStefan Weil2012-09-221-8/+2
| | | | | | | | | | | | | | | | | | | | | | 32 bit x86 hosts don't need registers for helper function arguments because they use the default stack based calling convention. Removing the registers allows simpler code for function tcg_target_get_call_iarg_regs_count. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | tcg/i386: Add shortcuts for registers used in L constraintStefan Weil2012-09-221-48/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While 64 bit hosts use the first three registers which are also used as function input parameters, 32 bit hosts use TCG_REG_EAX and TCG_REG_EDX which are not used in parameter passing. After defining new register macros for the registers used in L constraint, the patch replaces most occurrences of tcg_target_call_iarg_regs[0], tcg_target_call_iarg_regs[1] and tcg_target_call_iarg_regs[2] by those new macros. tcg_target_call_iarg_regs remains unchanged when it is used for input arguments (only with 64 bit hosts) before tcg_out_calli. A comment related to those registers was fixed, too. Signed-off-by: Stefan Weil <sw@weilnetz.de> [aurel32: build fix on i386, small optimization for i386 in the prologue] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | w64: Fix TCG helper functions with 5 argumentsStefan Weil2012-09-222-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TCG uses 6 registers for function arguments on 64 bit Linux hosts, but only 4 registers on W64 hosts. Commit 2999a0b20074a7e4a58f56572bb1436749368f59 increased the number of arguments for some important helper functions from 4 to 5 which triggered a bug for W64 hosts: QEMU aborts when executing helper_lcall_real in the guest's BIOS because function tcg_target_get_call_iarg_regs_count always returned 6. As W64 has only 4 registers for arguments, the 5th argument must be passed on the stack using a correct stack offset. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | tcg/README: document tcg_gen_goto_tb restrictionsMax Filippov2012-09-221-1/+2
| | | | | | | | | | | | | | | | | | See http://lists.nongnu.org/archive/html/qemu-devel/2012-09/msg03196.html for the whole story. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | tcg-hppa: Implement movcondRichard Henderson2012-09-222-1/+22
| | | | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | tcg/optimize: add constant folding for depositAurelien Jarno2012-09-221-0/+20
| | | | | | | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | tcg: remove #ifdef #endif around TCGOpcode testsAurelien Jarno2012-09-221-12/+1
| | | | | | | | | | | | | | | | | | Commit 25c4d9cc changed all TCGOpcode enums to be available, so we don't need to #ifdef #endif the one that are available only on some targets. This makes the code easier to read. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | tcg/optimize: prefer the "op a, a, b" form for commutative opsAurelien Jarno2012-09-221-1/+4
| | | | | | | | | | | | | | | | | | | | | | The "op a, a, b" form is better handled on non-RISC host than the "op a, b, a" form, so swap the arguments to this form when possible, and when b is not a constant. This reduces the number of generated instructions by a tiny bit. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | tcg/optimize: further optimize brcond/movcond/setcondAurelien Jarno2012-09-221-51/+76
| | | | | | | | | | | | | | | | | | When both argument of brcond/movcond/setcond are the same or when one of the two values is a constant equal to zero, it's possible to do further optimizations. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | tcg/optimize: optimize "op r, a, a => movi r, 0"Aurelien Jarno2012-09-221-0/+16
| | | | | | | | | | | | | | | | | | Now that it's possible to detect copies, we can optimize the case the "op r, a, a => movi r, 0". This helps in the computation of overflow flags when one of the two args is 0. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | tcg/optimize: optimize "op r, a, a => mov r, a"Aurelien Jarno2012-09-221-1/+1
| | | | | | | | | | | | | | | | Now that we can easily detect all copies, we can optimize the "op r, a, a => mov r, a" case a bit more. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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