summaryrefslogtreecommitdiffstats
path: root/tcg/tcg-opc.h
Commit message (Collapse)AuthorAgeFilesLines
* tcg: Always define all of the TCGOpcode enum members.Richard Henderson2011-08-211-154/+88
| | | | | | | | | | | | By always defining these symbols, we can eliminate a lot of ifdefs. To allow this to be checked reliably, the semantics of the TCG_TARGET_HAS_* macros must be changed from def/undef to true/false. This allows even more ifdefs to be removed, converting them into C if statements. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Add and use TCG_OPF_64BIT.Richard Henderson2011-08-211-49/+49
| | | | | | | | This allows the simplification of the op_bits function from tcg/optimize.c. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Define "deposit" as an optional operation.Richard Henderson2011-01-201-0/+6
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* tcg: get rid of DEF2 in tcg-opc.hAurelien Jarno2010-06-091-146/+147
| | | | | | | Now that tcg-opc.h is only used in TCG code, get rid of DEF2 in tcg-opc.h. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: get rid of copy_size in TCGOpDefAurelien Jarno2010-06-091-1/+1
| | | | | | copy_size is a left-over from the dyngen era, remove it. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson2010-03-261-2/+3
| | | | | | | | | | | | | | | Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands sign-extended in 64-bit registers (regardless of the "real" sign of the operand). For that, we need to be able to distinguish between a 32-bit load with a 32-bit result and a 32-bit load with a given extension to a 64-bit result. This distinction already exists for the ld* loads, but not the qemu_ld* loads. Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for 32-bit outputs. Adjust all code generators to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of NOR.Richard Henderson2010-03-261-0/+6
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of NAND.Richard Henderson2010-03-261-0/+6
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of EQV.Richard Henderson2010-03-261-0/+6
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: protect div2 in tcg/tcg-opc.hAurelien Jarno2010-03-201-2/+4
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: fix assertion with --enable-debugJay Foad2010-02-201-5/+0
| | | | | | | | | | | On 32-bit hosts op_qemu_ld32s is unused. Remove it to fix the following assertion failure: qemu-alpha: tcg/tcg.c:1055: tcg_add_target_add_op_defs: Assertion `tcg_op_defs[op].used' failed. Signed-off-by: Jay Foad <jay.foad@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Optional target implementation of ORC.Richard Henderson2010-02-201-0/+6
| | | | | | | | Previously ORC was always implemented by tcg-op.h with an explicit NOT opcode. Allow a target implementation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Optional target implementation of ANDC.Richard Henderson2010-02-201-0/+6
| | | | | | | | Previously ANDC was always implemented by tcg-op.h with an explicit NOT opcode. Allow a target implementation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: generic support for conditional setRichard Henderson2010-02-061-0/+3
| | | | | | | Defines setcond_{i32,i64} and setcond2_i32 for 64-on-32-bit. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: add ext{8,16,32}u_i{32,64} TCG opsAurelien Jarno2009-10-041-0/+15
| | | | | | | | | | | | | | | | | | | | | Currently zero extensions ops are implemented by a and op with a constant. This is then catched in some backend, and replaced by a zero extension instruction. While this works well on RISC machines, this adds a useless register move on non-RISC machines. Example on x86: ext16u_i32 r1, r2 is translated into mov %eax,%ebx movzwl %bx, %ebx while the optimized version should be: movzwl %ax, %ebx This patch adds ext{8,16,32}u_i{32,64} TCG ops that can be implemented in the backends to avoid emitting useless register moves. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: add bswap16_i64 and bswap32_i64 TCG opsaurel322009-03-131-0/+6
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6832 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg: allow bswap16_i32 to be implemented by TCG backendsaurel322009-03-131-0/+3
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6830 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg: rename bswap_i32/i64 functionsaurel322009-03-131-4/+4
| | | | | | | | Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg: move {not,neg}_i{32,64} definitions at the right placeaurel322009-03-111-7/+7
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6811 c046a42c-6fe2-441c-8c8c-71466251a162
* Implement TCG not ops for x86-64aurel322009-03-091-0/+6
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6797 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg: don't define TCG rotation ops if they are not supportedaurel322009-03-091-0/+4
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6796 c046a42c-6fe2-441c-8c8c-71466251a162
* Implement TCG rotation ops for x86-64aurel322009-03-091-2/+6
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6795 c046a42c-6fe2-441c-8c8c-71466251a162
* Some cleanups after dyngen removalaurel322008-12-071-4/+0
| | | | | | | | | | | | | | | | | | | this patch removes some now unused things after dyngen removal. 1. dyngen-exec.h: op_param, op _jmp and some associated macros are now unused; 2. Makefile.target: tcg-dyngen is not needed anymore 2. tcg/tcg-op.h, tcg/tcg-opc.h: gen-op.h is dead 3. tcg.c: - INDEX_op_end is now the first op - CONFIG_DYNGEN_OP is never defined 4. tcg.h: dyngen_op not needed anymore 5. exec-all.h: remove some ASM macros. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5922 c046a42c-6fe2-441c-8c8c-71466251a162
* suppressed unused macro handlingbellard2008-05-251-5/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4580 c046a42c-6fe2-441c-8c8c-71466251a162
* added debug_insn_start debug instructionbellard2008-05-221-0/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4531 c046a42c-6fe2-441c-8c8c-71466251a162
* Add TCG native negation op.pbrook2008-05-111-0/+6
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4426 c046a42c-6fe2-441c-8c8c-71466251a162
* Rename CONFIG_NO_DYNGEN_OP to CONFIG_DYNGEN_OP to avoid double negativesblueswir12008-05-101-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4412 c046a42c-6fe2-441c-8c8c-71466251a162
* Prepare for op.c removal and zero legacy opsblueswir12008-03-211-0/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4095 c046a42c-6fe2-441c-8c8c-71466251a162
* fixed sign extensions - added explicit side effect op flag - added discard ↵bellard2008-02-041-48/+50
| | | | | | instruction git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3963 c046a42c-6fe2-441c-8c8c-71466251a162
* TCG code generatorbellard2008-02-011-0/+228
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3943 c046a42c-6fe2-441c-8c8c-71466251a162
OpenPOWER on IntegriCloud