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* tcg: make tcg_const_ptr actually accept a pointer argumentPeter Maydell2011-12-141-3/+3
| | | | | | | | | | Make tcg_const_ptr() include a cast so that you can pass it a pointer. This allows us to drop the casts we had in all the places that use this macro. Acked-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* tcg: Fix whitespace in tcg-op.h.Richard Henderson2011-11-021-4/+4
| | | | | | | Removing the only tabs in the file. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: malc <av1474@comtv.ru>
* tcg: Fix regression in tcg_gen_deposit_i64.Richard Henderson2011-11-021-0/+2
| | | | | | | | The error being caused by the failure to copy the other half of the input to the output after having narrowed the deposit operation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: malc <av1474@comtv.ru>
* tcg: Optimize some forms of deposit.Richard Henderson2011-10-301-14/+51
| | | | | | | | | | | | | If the deposit replaces the entire word, optimize to a move. If we're inserting to the top of the word, avoid the mask of arg2 as we'll be shifting out all of the garbage and shifting in zeros. If the host is 32-bit, reduce a 64-bit deposit to a 32-bit deposit when possible. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg-i386: Introduce limited deposit supportJan Kiszka2011-10-011-2/+2
| | | | | | | | | | | | x86 cannot provide an optimized generic deposit implementation. But at least for a few special cases, namely for writing bits 0..7, 8..15, and 0..15, versions using only a single instruction are feasible. Introducing such limited support improves emulating 16-bit x86 code on x86, but also rarer cases where 32-bit or 64-bit code accesses bytes or words. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Always define all of the TCGOpcode enum members.Richard Henderson2011-08-211-500/+446
| | | | | | | | | | | | By always defining these symbols, we can eliminate a lot of ifdefs. To allow this to be checked reliably, the semantics of the TCG_TARGET_HAS_* macros must be changed from def/undef to true/false. This allows even more ifdefs to be removed, converting them into C if statements. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: If DEBUG_TCGV, distinguish TCGv_ptr from TCGv_i32/TCGv_i64Peter Maydell2011-06-031-10/+16
| | | | | | | | | | | | | When compiling with DEBUG_TCGV enabled, make the TCGv_ptr type distinct from TCGv_i32/TCGv_i64. This means that using an i32 or i64 TCG op to manipulate a TCGv_ptr will always be detected at compile time, rather than only if compiling on a host system with the other word size. NB: the tcg_add_ptr and tcg_sub_ptr macros have been removed as they were not used anywhere. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/tcg-op.h: Fix prototypes for ld/st functions on 64 bit hostsPeter Maydell2011-06-031-11/+11
| | | | | | | | | | The prototypes for the ld/st functions on a 64 bit host declared the address parameter as a TCGv_i64 rather than a TCGv_ptr. This worked OK (since the two are aliases), but needs to be fixed to allow extension of TCG type debugging to i64/i32/ptr mismatches. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Define "deposit" as an optional operation.Richard Henderson2011-01-201-0/+64
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* tcg: Fix default definition of divu_i32 and remu_i32.Richard Henderson2010-12-011-2/+2
| | | | | | | | The arguments to tcg_gen_helper32 for these functions were not updated correctly in rev 2bece2c88331f024a46527634e3dd91c71d22141. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
* tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.Richard Henderson2010-06-161-21/+118
| | | | | | | | | | | | | | | | | | Some hosts (amd64, ia64) have an ABI that ignores the high bits of the 64-bit register when passing 32-bit arguments. Others require the value to be properly sign-extended for the type. I.e. "int32_t" must be sign-extended and "uint32_t" must be zero-extended to 64-bits. To effect this, extend the "sizemask" parameter to tcg_gen_callN to include the signedness of the type of each parameter. If the tcg target requires it, extend each 32-bit argument into a 64-bit temp and pass that to the function call. This ABI feature is required by sparc64, ppc64 and s390x. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Use INDEX_op_qemu_ld32 for 32-bit results.Richard Henderson2010-05-281-0/+8
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson2010-03-261-4/+4
| | | | | | | | | | | | | | | Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands sign-extended in 64-bit registers (regardless of the "real" sign of the operand). For that, we need to be able to distinguish between a 32-bit load with a 32-bit result and a 32-bit load with a given extension to a 64-bit result. This distinction already exists for the ld* loads, but not the qemu_ld* loads. Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for 32-bit outputs. Adjust all code generators to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of NOR.Richard Henderson2010-03-261-0/+11
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of NAND.Richard Henderson2010-03-261-0/+11
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of EQV.Richard Henderson2010-03-261-0/+11
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Use not_i32 to implement not_i64.Richard Henderson2010-03-261-0/+3
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Change TCGType to an enumeration.Richard Henderson2010-03-261-2/+0
| | | | | | | The TCGType name was already used consistently. Changing it to an enumeration instead of a set of defines aids debugging. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Use TCGCond where appropriate.Richard Henderson2010-03-261-17/+17
| | | | | | | | Use the TCGCond enumeration type in the brcond and setcond related prototypes in tcg-op.h and each code generator. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Name the opcode enumeration.Richard Henderson2010-03-261-42/+42
| | | | | | | | Give the enumeration formed from tcg-opc.h a name: TCGOpcode. Use that enumeration type instead of "int" whereever appropriate. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: declare internal helpers as const and pureAurelien Jarno2010-03-141-4/+9
| | | | | | | | TCG internal helpers only access to the values passed in arguments, and do not modify the CPU internal state. Thus they can be declared as const and pure. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: add div/rem 32-bit helpersAurelien Jarno2010-03-141-2/+55
| | | | | | | | | | | Some targets like ARM would benefit to use 32-bit helpers for div/rem/divu/remu. Create a #define for div2 so that targets can select between div, div2 and helper implementation. Use the helper version if none of the #define are present. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Optional target implementation of ORC.Richard Henderson2010-02-201-0/+11
| | | | | | | | Previously ORC was always implemented by tcg-op.h with an explicit NOT opcode. Allow a target implementation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Optional target implementation of ANDC.Richard Henderson2010-02-201-0/+11
| | | | | | | | Previously ANDC was always implemented by tcg-op.h with an explicit NOT opcode. Allow a target implementation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: move setcond* ops to non-optional sectionAurelien Jarno2010-02-081-35/+37
| | | | | | setcond is not an optional op, move it to the non-optional section. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: add setcondi pseudo-opAurelien Jarno2010-02-081-0/+18
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: generic support for conditional setRichard Henderson2010-02-061-0/+47
| | | | | | | Defines setcond_{i32,i64} and setcond2_i32 for 64-on-32-bit. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: add ext{8,16,32}u_i{32,64} TCG opsAurelien Jarno2009-10-041-3/+21
| | | | | | | | | | | | | | | | | | | | | Currently zero extensions ops are implemented by a and op with a constant. This is then catched in some backend, and replaced by a zero extension instruction. While this works well on RISC machines, this adds a useless register move on non-RISC machines. Example on x86: ext16u_i32 r1, r2 is translated into mov %eax,%ebx movzwl %bx, %ebx while the optimized version should be: movzwl %ax, %ebx This patch adds ext{8,16,32}u_i{32,64} TCG ops that can be implemented in the backends to avoid emitting useless register moves. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: fix size of local variables in tcg_gen_bswap64_i64Stefan Weil2009-09-161-5/+4
| | | | | | | t0, t1 must be 64 bit values, not 32 bit. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Fix tcg_gen_rotr_i64Aurelien Jarno2009-07-181-1/+1
| | | | | Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: fix _tl aliases for divu/remuaurel322009-03-291-4/+4
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6948 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg: add _tl aliases for div/divu/rem/remuaurel322009-03-291-0/+8
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6939 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg: add _tl aliases to bswap16/32/64 TCG opsaurel322009-03-131-0/+5
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6833 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg: add bswap16_i64 and bswap32_i64 TCG opsaurel322009-03-131-0/+58
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6832 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg: optimize tcg_gen_bswap16_i32aurel322009-03-131-8/+5
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6831 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg: rename bswap_i32/i64 functionsaurel322009-03-131-9/+9
| | | | | | | | Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg: fix commit r6805aurel322009-03-111-18/+6
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6810 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg: optimize logical operationsaurel322009-03-101-50/+60
| | | | | | | | Simplify nand/nor/eqv and move their optimizations to and/or/xor Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6805 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix tcg after commit 6800aurel322009-03-101-1/+1
| | | | | | | | | | The introduction of TCGV_EQUAL and not op is slightly broken. The definition of DEBUG_TCGV shows that. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6802 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg: use TCGV_EQUAL_I{32,64}aurel322009-03-101-11/+11
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6800 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg: optimize nor(X, Y, Y), used on PPC for not(X, Y)aurel322009-03-091-10/+18
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6798 c046a42c-6fe2-441c-8c8c-71466251a162
* Implement TCG not ops for x86-64aurel322009-03-091-0/+8
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6797 c046a42c-6fe2-441c-8c8c-71466251a162
* Implement TCG rotation ops for x86-64aurel322009-03-091-0/+28
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6795 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix DEBUG_TCGV compile error.aurel322009-02-091-1/+1
| | | | | | | | | | Don't call TCGV_LOW on arg2. This section of code falls under Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6585 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg_temp_local_new should take no parameteraurel322009-01-011-2/+2
| | | | | | | | | | | | This patch removes useless type information in some calls to tcg_temp_local_new. It also removes the parameter from the macro declaration; if a target has to use a specific non-default size then it should use tcg_temp_local_new_{i32,i64}. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6146 c046a42c-6fe2-441c-8c8c-71466251a162
* Remove unnecessary trailing newlinesblueswir12008-12-131-1/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162
* Some cleanups after dyngen removalaurel322008-12-071-5/+0
| | | | | | | | | | | | | | | | | | | this patch removes some now unused things after dyngen removal. 1. dyngen-exec.h: op_param, op _jmp and some associated macros are now unused; 2. Makefile.target: tcg-dyngen is not needed anymore 2. tcg/tcg-op.h, tcg/tcg-opc.h: gen-op.h is dead 3. tcg.c: - INDEX_op_end is now the first op - CONFIG_DYNGEN_OP is never defined 4. tcg.h: dyngen_op not needed anymore 5. exec-all.h: remove some ASM macros. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5922 c046a42c-6fe2-441c-8c8c-71466251a162
* Some fixes for TCG debuggingblueswir12008-12-071-2/+2
| | | | | | | | | | | | | This fixes a few things after Paul's improvements for TCG debugging: - change TCGv_i64 field name to something different from TCGv_i32 - fix things in tcg that the above change made visible. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5919 c046a42c-6fe2-441c-8c8c-71466251a162
* TCG variable type checking.pbrook2008-11-171-697/+789
| | | | | | | Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix rotri_i64 typo.pbrook2008-11-031-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5609 c046a42c-6fe2-441c-8c8c-71466251a162
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