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* tcg: rename trunc_shr_i32 into trunc_shr_i64_i32Aurelien Jarno2015-08-242-3/+3
| | | | | | | | | | | The op is sometimes named trunc_shr_i32 and sometimes trunc_shr_i64_i32, and the name in the README doesn't match the name offered to the frontends. Always use the long name to make it clear it is a size changing op. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Mask TCGMemOp appropriately for indexingRichard Henderson2015-06-091-15/+15
| | | | | | | | | | The addition of MO_AMASK means that places that used inverted masks need to be changed to use positive masks, and places that failed to mask the intended bits need updating. Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Tested-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: add TCG_TARGET_TLB_DISPLACEMENT_BITSPaolo Bonzini2015-06-031-0/+1
| | | | | | | | | | | | This will be used to size the TLB when more than 8 MMU modes are used by the target. Limitations come from the limited size of the immediate fields (which sometimes, as in the case of Aarch64, extend to instructions that shift the immediate). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1424436345-37924-2-git-send-email-pbonzini@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* tcg: Push merged memop+mmu_idx parameter to softmmu routinesRichard Henderson2015-05-141-3/+3
| | | | | | | | The extra information is not yet used but it is now available. This requires minor changes through all of the tcg backends. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Merge memop and mmu_idx parameters to qemu_ld/stRichard Henderson2015-05-141-5/+9
| | | | | | | | | At the tcg opcode level, not at the tcg-op.h generator level. This requires minor changes through all of the tcg backends, but none of the cpu translators. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Change generator-side labels to a pointerRichard Henderson2015-03-131-12/+10
| | | | | | | | | | | | | | | This is less about improved type checking than enabling a subsequent change to the representation of labels. Acked-by: Claudio Fontana <claudio.fontana@huawei.com> Tested-by: Claudio Fontana <claudio.fontana@huawei.com> Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Stefan Weil <sw@weilnetz.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Use UMULXHI instructionRichard Henderson2014-09-292-1/+6
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Rename ADDX/SUBX insnsRichard Henderson2014-09-291-7/+7
| | | | | | | The pre-v9 ADDX/SUBX insns were renamed ADDC/SUBC for v9. Standardizing on the v9 name makes things less confusing. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Use ADDXC in setcond_i64Richard Henderson2014-09-291-0/+17
| | | | | | Similar to the ADDC tricks we use in setcond_i32. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Fix setcond_i32 uninitialized valueRichard Henderson2014-09-291-2/+5
| | | | | | We failed to swap c1 and c2 correctly for NE c2 == 0. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Use ADDXC in addsub2_i64Richard Henderson2014-09-292-5/+29
| | | | | | | On T4 and newer Sparc chips we have an add-with-carry insn that takes its input from %xcc instead of %icc. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Support addsub2_i64Richard Henderson2014-09-292-9/+67
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Remove TCG_TARGET_HAS_new_ldstRichard Henderson2014-06-041-2/+0
| | | | | | | Since all backends have been converted, remove the compatibility code. Acked-by: Claudio Fontana <claudio.fontana@huawei.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Make debug_frame constRichard Henderson2014-05-281-13/+9
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Remove unreachable code in tcg_out_op and op_defsRichard Henderson2014-05-121-18/+3
| | | | | | | | | | | The INDEX_op_call case has just been obsoleted; the mov and movi cases have not been reachable for years. Attempt to document this both in each tcg_out_op switch, and via TCG_OPF_NOT_PRESENT. Because of the TCG_OPF_NOT_PRESENT change, this must be done for all targets in a single commit. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Create tcg_out_callRichard Henderson2014-05-121-8/+14
| | | | | | Rename the existing tcg_out_calli to tcg_out_call_nodelay. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson2014-05-122-69/+60
| | | | | | | And use tcg pointer differencing functions as appropriate. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Accept stores of zeroRichard Henderson2014-04-281-2/+2
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Fix small 32-bit moviRichard Henderson2014-04-281-0/+5
| | | | | | We tested imm13 before discarding garbage high bits. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Fixup function argument typesRichard Henderson2014-04-281-66/+51
| | | | | | | | Use TCGReg everywhere appropriate. Use int32_t for all arguments that may be registers or immediate constants. Merge tcg_out_addi into its only caller. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Hoist common argument loads in tcg_out_opRichard Henderson2014-04-281-63/+60
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Don't handle mov/movi in tcg_out_opRichard Henderson2014-04-281-7/+6
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Tidy check_fit_* testsRichard Henderson2014-04-281-15/+20
| | | | | | | Use sextract instead of raw bit shifting for the tests. Introduce a new check_fit_ptr macro to make it clear we're looking at pointers. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Implement muls2_i32Richard Henderson2014-04-282-4/+16
| | | | | | | Using the 32-bit SMUL is a tad more efficient than resorting to extending and using the 64-bit MULX. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Use the RETURN instructionRichard Henderson2014-04-281-4/+10
| | | | | | Saves one insn per TB exit over JMPL+RESTORE. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Use 64-bit registers with sparcv8plusRichard Henderson2014-04-282-354/+185
| | | | | | | | Quite a lot of effort was spent composing and decomposing 64-bit quantities in registers, when we should just create them and leave them as one 64-bit register. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Support trunc_shr_i32Richard Henderson2014-04-282-1/+9
| | | | | | | Unlike a 64-bit shift op, allows the output to be in %l or %i registers for sparcv8plus. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Remove most uses of TCG_TARGET_REG_BITSRichard Henderson2014-04-281-33/+37
| | | | | | | Replace with SPARC64 define. Soon even sparcv8plus will use 64-bit register as far as TCG is concerned. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add INDEX_op_trunc_shr_i32Richard Henderson2014-04-281-0/+1
| | | | | | Let the backend do something special for truncation. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Use HOST_WORDS_BIGENDIANRichard Henderson2014-04-181-2/+0
| | | | | | Instead of rolling a local TCG_TARGET_WORDS_BIGENDIAN. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Use the type parameter to tcg_target_const_matchRichard Henderson2014-04-181-1/+7
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add TCGType parameter to tcg_target_const_matchRichard Henderson2014-04-181-1/+1
| | | | | | | | Most 64-bit targets need to be able to ignore the high bits of a TCG_TYPE_I32 value. Suggested-by: Stuart Brady <sdb@zubnet.me.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Convert to new ldst opcodesRichard Henderson2014-03-172-100/+53
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Convert to new ldst helpersRichard Henderson2014-03-171-59/+131
| | | | | | | | | | All of the helpers with the explicit big/little endian option require the return address as a parameter. Acquire this via a trampoline. Move the load of areg0 into the trampoline. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Tidy tcg_out_tlb_load interfaceRichard Henderson2014-03-171-40/+30
| | | | | | | Pass address registers explicitly, rather than as indicies of args[]. It's two argument registers either way. Use more TCGReg as appropriate. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Use TCGMemOp within qemu_ldst routinesRichard Henderson2014-03-171-51/+65
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Improve tcg_out_moviRichard Henderson2014-03-171-21/+31
| | | | | | If bits 31:13 are zero, reduce the insn count by one. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Dont handle constant arguments to ext32 opsRichard Henderson2014-03-171-12/+4
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Don't handle remainderRichard Henderson2014-03-172-23/+2
| | | | | | The generic fallback is exactly what we implemented. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Use intptr_t as appropriateRichard Henderson2014-03-171-11/+9
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Tidy call+jump patternsRichard Henderson2014-03-171-19/+19
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Fix tlb readRichard Henderson2014-03-171-21/+15
| | | | | | | | We were computing the full address into %o0 and then not using it. Adjust some of the computation to rely less on having to pull immediate values into registers. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Fix ld64 for 32-bit modeRichard Henderson2014-03-171-0/+1
| | | | | | | Since were not using an annulled branch, we need to put a nop in the delay slot. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add qemu_ld_st_i32/64Richard Henderson2013-10-101-0/+2
| | | | | | | Step two in the transition, adding the new ldst opcodes. Keep the old opcodes around until all backends support the new opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add tcg-be-null.hRichard Henderson2013-10-101-0/+2
| | | | | | | | | This is a no-op backend data implementation, for those targets that are not currently using the load/store optimization path. This is prepatory to always requiring these functions in all backends. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Fix parenthesis warningRichard Henderson2013-09-201-1/+1
| | | | | | | error: suggest parentheses around comparison in operand of ‘&’ [-Werror=parentheses] Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* exec: Split softmmu_defs.hRichard Henderson2013-09-021-2/+0
| | | | | | | | | | | The _cmmu helpers can be moved to exec-all.h. The helpers that are used from TCG will shortly need access to tcg_target_long so move their declarations into tcg.h. This requires minor include adjustments to all TCG backends. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Change tcg_out_ld/st offset to intptr_tRichard Henderson2013-09-021-2/+2
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Change relocation offsets to intptr_tRichard Henderson2013-09-021-3/+3
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Allow TCG_TARGET_REG_BITS to be specified independantlyRichard Henderson2013-09-021-0/+8
| | | | | | | | There are several hosts for which it would be useful to use the available 64-bit registers in a 32-bit pointer environment. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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