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* tcg: add TCG_TARGET_TLB_DISPLACEMENT_BITSPaolo Bonzini2015-06-031-0/+1
| | | | | | | | | | | | This will be used to size the TLB when more than 8 MMU modes are used by the target. Limitations come from the limited size of the immediate fields (which sometimes, as in the case of Aarch64, extend to instructions that shift the immediate). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1424436345-37924-2-git-send-email-pbonzini@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* tcg: Push merged memop+mmu_idx parameter to softmmu routinesRichard Henderson2015-05-141-12/+11
| | | | | | | | The extra information is not yet used but it is now available. This requires minor changes through all of the tcg backends. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Merge memop and mmu_idx parameters to qemu_ld/stRichard Henderson2015-05-141-4/+8
| | | | | | | | | At the tcg opcode level, not at the tcg-op.h generator level. This requires minor changes through all of the tcg backends, but none of the cpu translators. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Change generator-side labels to a pointerRichard Henderson2015-03-131-17/+14
| | | | | | | | | | | | | | | This is less about improved type checking than enabling a subsequent change to the representation of labels. Acked-by: Claudio Fontana <claudio.fontana@huawei.com> Tested-by: Claudio Fontana <claudio.fontana@huawei.com> Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Stefan Weil <sw@weilnetz.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Remove TCG_TARGET_HAS_new_ldstRichard Henderson2014-06-041-2/+0
| | | | | | | Since all backends have been converted, remove the compatibility code. Acked-by: Claudio Fontana <claudio.fontana@huawei.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Make debug_frame constRichard Henderson2014-05-281-13/+9
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Implement direct chaining of TBsRichard Henderson2014-05-151-1/+3
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Improve setcondRichard Henderson2014-05-151-6/+91
| | | | | | | | There are a variety of common cases for which we can use carry tricks to avoid a conditional branch. On very new hardware, use LOAD ON CONDITION instead of a conditional branch. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Allow immediate operands to add2 and sub2Richard Henderson2014-05-151-12/+52
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Implement tcg_register_jitRichard Henderson2014-05-151-7/+55
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Use more risbg in the tlb sequenceRichard Henderson2014-05-151-21/+28
| | | | | | | | | | | | | Elides two insns from the sequence. The resulting tlb compare sequence is satisfyingly minimal: risbg %r2,%r8,51,186,56 risbg %r3,%r8,61,178,0 cg %r3,904(%r10,%r2) lg %r2,920(%r10,%r2) jlh tlb_miss Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Move ldst helpers out of lineRichard Henderson2014-05-151-92/+118
| | | | | | That is, the old LDST_OPTIMIZATION. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Convert to new ldst opcodesRichard Henderson2014-05-152-116/+56
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Integrate endianness into TCGMemOpRichard Henderson2014-05-151-64/+60
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Convert to TCGMemOpRichard Henderson2014-05-151-46/+36
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Fix off-by-one in wraparound andiRichard Henderson2014-05-151-2/+2
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Remove unreachable code in tcg_out_op and op_defsRichard Henderson2014-05-121-30/+5
| | | | | | | | | | | The INDEX_op_call case has just been obsoleted; the mov and movi cases have not been reachable for years. Attempt to document this both in each tcg_out_op switch, and via TCG_OPF_NOT_PRESENT. Because of the TCG_OPF_NOT_PRESENT change, this must be done for all targets in a single commit. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Rename tgen_calli to tcg_out_callRichard Henderson2014-05-121-4/+4
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson2014-05-122-48/+45
| | | | | | And use tcg pointer differencing functions as appropriate. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add INDEX_op_trunc_shr_i32Richard Henderson2014-04-281-0/+1
| | | | | | Let the backend do something special for truncation. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Use HOST_WORDS_BIGENDIANRichard Henderson2014-04-181-2/+0
| | | | | | Instead of rolling a local TCG_TARGET_WORDS_BIGENDIAN. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Remove W constraintRichard Henderson2014-04-181-24/+19
| | | | | | Now redundant with the type parameter to tcg_target_const_match. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add TCGType parameter to tcg_target_const_matchRichard Henderson2014-04-181-1/+1
| | | | | | | | Most 64-bit targets need to be able to ignore the high bits of a TCG_TYPE_I32 value. Suggested-by: Stuart Brady <sdb@zubnet.me.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/s390: Remove sigill_handlerRichard Henderson2014-02-011-19/+0
| | | | | | | | | Commit c9baa30f42a87f61627391698f63fa4d1566d9d8 failed to delete all of the relevant code, leading to Werrors about unused symbols. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* tcg-s390: Use qemu_getauxval in query_facilitiesRichard Henderson2013-11-301-83/+12
| | | | | | | | | | No need to set up a SIGILL signal handler for detection anymore. Remove a ton of sanity checks that must be true, given that we're requiring a 64-bit build (the note about 31-bit KVM is satisfied by configuring with TCI). Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add qemu_ld_st_i32/64Richard Henderson2013-10-101-0/+2
| | | | | | | Step two in the transition, adding the new ldst opcodes. Keep the old opcodes around until all backends support the new opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add tcg-be-null.hRichard Henderson2013-10-101-0/+2
| | | | | | | | | This is a no-op backend data implementation, for those targets that are not currently using the load/store optimization path. This is prepatory to always requiring these functions in all backends. Signed-off-by: Richard Henderson <rth@twiddle.net>
* exec: Split softmmu_defs.hRichard Henderson2013-09-021-3/+0
| | | | | | | | | | | The _cmmu helpers can be moved to exec-all.h. The helpers that are used from TCG will shortly need access to tcg_target_long so move their declarations into tcg.h. This requires minor include adjustments to all TCG backends. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Change tcg_out_ld/st offset to intptr_tRichard Henderson2013-09-021-2/+2
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Change relocation offsets to intptr_tRichard Henderson2013-09-021-3/+3
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Change flush_icache_range arguments to uintptr_tRichard Henderson2013-09-021-2/+1
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add muluh and mulsh opcodesRichard Henderson2013-09-021-0/+4
| | | | | | | | Use them in places where mulu2 and muls2 are used. Optimize mulx2 with dead low part to mulxh. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Remove redundant tcg_target_init checksRichard Henderson2013-06-051-7/+0
| | | | | | | | We've got a compile-time check for the condition in exec/cpu-defs.h. Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: liguang <lig.fnst@cn.fujitsu.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Fix merge error in tgen_brcondRichard Henderson2013-04-051-1/+1
| | | | | | | When the TCG condition codes were re-organized last year, we failed to update all of the "old-style" tests for unsigned. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Use all 20 bits of the offset in tcg_out_memRichard Henderson2013-04-051-4/+5
| | | | | | | This can save one insn, if the constant has any bits in 32-63 set, but no bits in 21-31 set. It never results in more insns. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Use load-address for additionRichard Henderson2013-04-051-57/+56
| | | | | | | | Since we're always in 64-bit mode, load address performs a full 64-bit add. Use that for 3-address addition, as well as for larger constant addends when we lack extended-immediates facility. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Cleanup argument shuffling fixme in softmmu codeRichard Henderson2013-04-051-47/+38
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Use risbgz for andiRichard Henderson2013-04-051-5/+53
| | | | | | This is immediately usable by the tlb lookup code. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Remove constraint letters for andRichard Henderson2013-04-051-117/+32
| | | | | | | Since we have a free temporary and can always just load the constant, we ought to do so, rather than spending the same effort constraining the const. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Implement deposit opcodesRichard Henderson2013-04-052-2/+30
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Implement movcond opcodesRichard Henderson2013-04-052-4/+41
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Implement mulu2_i64 opcodeRichard Henderson2013-04-052-1/+6
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Implement add2/sub2 opcodesRichard Henderson2013-04-052-4/+42
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Remove useless preprocessor conditionsRichard Henderson2013-04-052-14/+5
| | | | | | | We only support 64-bit code generation for s390x. Don't clutter the code with ifdefs that suggest otherwise. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Properly allocate a stack frame.Richard Henderson2013-04-052-7/+15
| | | | | | | | Set TCG_TARGET_CALL_STACK_OFFSET properly for the abi. Allocate the standard TCG_STATIC_CALL_ARGS_SIZE. And while we're at it, allocate space for CPU_TEMP_BUF_NLONGS. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Fix moviRichard Henderson2013-04-051-1/+1
| | | | | The code to load the high 64 bits assumed that the insn used to load the low 64 bits zero-extended. Enforce that.
* tcg: Add signed multiword multiplication operationsRichard Henderson2013-02-231-0/+2
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Add 64-bit multiword arithmetic operationsRichard Henderson2013-02-231-0/+3
| | | | | | Matching the 32-bit multiword arithmetic that we already have. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Make 32-bit multiword operations optional for 64-bit hostsRichard Henderson2013-02-231-0/+3
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* exec: move include files to include/exec/Paolo Bonzini2012-12-191-1/+1
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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