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* tcg/ppc32: implement deposit_i32malc2011-08-222-1/+13
* tcg: Always define all of the TCGOpcode enum members.Richard Henderson2011-08-211-15/+16
* TCG/PPC: use stack for TCG tempsBlue Swirl2011-06-281-2/+5
* tcg/ppc: Remove tcg_out_addimalc2011-06-281-5/+0
* Delegate setup of TCG temporaries to targetsBlue Swirl2011-06-261-0/+2
* cpu-exec.c: avoid AREG0 useBlue Swirl2011-06-261-3/+3
* TCG: Fix Darwin/ppc calling convention recognitionAndreas Färber2010-08-151-1/+1
* tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.Richard Henderson2010-06-291-4/+4
* tcg: Make some tcg-target.c routines static.Richard Henderson2010-06-091-2/+2
* tcg: Add TYPE parameter to tcg_out_mov.Richard Henderson2010-06-091-24/+24
* tcg/ppc: Remove redundant comparison from brcond2malc2010-04-181-2/+1
* tcg/ppc: Fix signed versions of brcond2malc2010-04-171-1/+2
* tcg/ppc: Fix typomalc2010-04-061-1/+1
* tcg/ppc: Implment bswap16/32malc2010-04-062-2/+77
* tcg/ppc: Implement eqv, nand and normalc2010-04-052-3/+17
* Split TLB addend and target_phys_addr_tPaul Brook2010-04-051-10/+2
* tcg/ppc: Fix not_i32malc2010-04-041-1/+1
* tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson2010-03-261-3/+3
* tcg: Allow target-specific implementation of NOR.Richard Henderson2010-03-261-0/+1
* tcg: Allow target-specific implementation of NAND.Richard Henderson2010-03-261-0/+1
* tcg: Allow target-specific implementation of EQV.Richard Henderson2010-03-261-0/+1
* tcg: Use TCGCond where appropriate.Richard Henderson2010-03-261-3/+4
* tcg: Name the opcode enumeration.Richard Henderson2010-03-261-1/+1
* remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini2010-03-261-2/+0
* tcg/ppc[64]: Only define addend load helpers in softmmu casemalc2010-03-131-0/+3
* tcg/ppc: Fix right rotationmalc2010-02-271-1/+2
* tcg/ppc: Fix typomalc2010-02-231-1/+1
* tcg/ppc: Implement some of the optional opsmalc2010-02-222-8/+88
* tcg: fix build on 32-bit hppa, ppc and sparc hostsJay Foad2010-02-221-2/+0
* tcg: Add comments for all optional instructions not implemented.Richard Henderson2010-02-201-1/+9
* tcg/ppc: Consistently use calling convention selection macrosmalc2010-02-201-12/+12
* Use ppc host calling convention definitions to set TCG_TARGET_CALL_{ALIGN_ARG...Juergen Lock2010-02-201-3/+3
* tcg/ppc32: proper setcond implementationmalc2010-02-071-25/+25
* tcg/ppc32: implement setcond[2]malc2010-02-071-14/+157
* tcg/ppc: always use tcg_out_callmalc2009-09-271-20/+10
* When targeting PPU use rlwinm instead of andi. if possiblemalc2009-09-061-8/+54
* Fix rbase initializationmalc2009-07-201-1/+1
* PPC 32/64 GUEST_BASE supportmalc2009-07-182-21/+65
* Fix LHZX opcode valuemalc2009-07-181-1/+1
* Whack [LS]MWmalc2009-04-111-3/+0
* Remove reserved registers from tcg_target_reg_alloc_ordermalc2009-04-111-3/+0
* Prune unused TCG_AREGsblueswir12009-03-081-1/+0
* Add missing r24..r26 to calle save registersmalc2009-02-111-0/+5
* R13 is reserved for small data area pointer by SVR4 PPC ABImalc2009-01-261-0/+5
* Use the ARRAY_SIZE() macro where appropriate.malc2008-12-221-1/+1
* Introduce and use cache-utils.[ch]malc2008-12-101-21/+0
* Preliminary AIX supportmalc2008-11-182-2/+52
* Rename misnamed BACK_CHAIN_OFFSET to LR_OFFSETmalc2008-11-121-4/+4
* Add some missing static and const qualifiers, reg_names only used if NDEBUG setblueswir12008-10-051-0/+2
* Avoid clobbering input register in qemu_ld64+bswap+useronly casemalc2008-09-221-13/+6
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