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* TCG: Fix Darwin/ppc calling convention recognitionAndreas Färber2010-08-151-1/+1
| | | | | | | | | | | | 5da79c86a3744e3a901c7986c109dd06951befd2 broke compilation on Mac OS X v10.5 ppc. Apple's GCC 4.0.1 does not define _CALL_DARWIN. Recognize __APPLE__ again as well. Signed-off-by: Andreas F?rber <andreas.faerber@web.de> Cc: malc <av1474@comtv.ru> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: J?rgen Lock <nox@jelal.kn-bremen.de> Cc: Stefan Weil <weil@mail.berlios.de> Signed-off-by: malc <av1474@comtv.ru>
* tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.Richard Henderson2010-06-291-4/+4
| | | | | | | We need not reserve the register unless we're going to use it. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: malc <av1474@comtv.ru>
* tcg: Make some tcg-target.c routines static.Richard Henderson2010-06-091-2/+2
| | | | | | | | Both tcg_target_init and tcg_target_qemu_prologue are unused outside of tcg.c. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Add TYPE parameter to tcg_out_mov.Richard Henderson2010-06-091-24/+24
| | | | | | | | | | | | | | Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64 to perform the move at the proper width, which may elide a REX prefix. Introduce a TCG_TYPE_REG enumerator to represent the "native width" of the host register, and to distinguish the usage from "pointer data" as represented by the existing TCG_TYPE_PTR. Update all targets to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/ppc: Remove redundant comparison from brcond2malc2010-04-181-2/+1
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc: Fix signed versions of brcond2malc2010-04-171-1/+2
| | | | | | Thanks to: Alexander Graff, Thomas Gleixner and Andreas Faerber. Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc: Fix typomalc2010-04-061-1/+1
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc: Implment bswap16/32malc2010-04-062-2/+77
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc: Implement eqv, nand and normalc2010-04-052-3/+17
| | | | Signed-off-by: malc <av1474@comtv.ru>
* Split TLB addend and target_phys_addr_tPaul Brook2010-04-051-10/+2
| | | | | | | | | | | | | | Historically the qemu tlb "addend" field was used for both RAM and IO accesses, so needed to be able to hold both host addresses (unsigned long) and guest physical addresses (target_phys_addr_t). However since the introduction of the iotlb field it has only been used for RAM accesses. This means we can change the type of addend to unsigned long, and remove associated hacks in the big-endian TCG backends. We can also remove the host dependence from target_phys_addr_t. Signed-off-by: Paul Brook <paul@codesourcery.com>
* tcg/ppc: Fix not_i32malc2010-04-041-1/+1
| | | | | | | Thanks to Alexander Graf for bug report and a good reproducible test case. Signed-off-by: malc <av1474@comtv.ru>
* tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson2010-03-261-3/+3
| | | | | | | | | | | | | | | Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands sign-extended in 64-bit registers (regardless of the "real" sign of the operand). For that, we need to be able to distinguish between a 32-bit load with a 32-bit result and a 32-bit load with a given extension to a 64-bit result. This distinction already exists for the ld* loads, but not the qemu_ld* loads. Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for 32-bit outputs. Adjust all code generators to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of NOR.Richard Henderson2010-03-261-0/+1
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of NAND.Richard Henderson2010-03-261-0/+1
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of EQV.Richard Henderson2010-03-261-0/+1
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Use TCGCond where appropriate.Richard Henderson2010-03-261-3/+4
| | | | | | | | Use the TCGCond enumeration type in the brcond and setcond related prototypes in tcg-op.h and each code generator. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Name the opcode enumeration.Richard Henderson2010-03-261-1/+1
| | | | | | | | Give the enumeration formed from tcg-opc.h a name: TCGOpcode. Use that enumeration type instead of "int" whereever appropriate. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini2010-03-261-2/+0
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/ppc[64]: Only define addend load helpers in softmmu casemalc2010-03-131-0/+3
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc: Fix right rotationmalc2010-02-271-1/+2
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc: Fix typomalc2010-02-231-1/+1
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc: Implement some of the optional opsmalc2010-02-222-8/+88
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg: fix build on 32-bit hppa, ppc and sparc hostsJay Foad2010-02-221-2/+0
| | | | | | | The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64. Signed-off-by: Jay Foad <jay.foad@gmail.com> Signed-off-by: malc <av1474@comtv.ru>
* tcg: Add comments for all optional instructions not implemented.Richard Henderson2010-02-201-1/+9
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg/ppc: Consistently use calling convention selection macrosmalc2010-02-201-12/+12
| | | | Signed-off-by: malc <av1474@comtv.ru>
* Use ppc host calling convention definitions to set ↵Juergen Lock2010-02-201-3/+3
| | | | | | | | | | | | | TCG_TARGET_CALL_{ALIGN_ARGS,STACK_OFFSET}. New version after malc's comments. (This avoids having to do #if defined __linux__ || defined __FreeBSD__ || defined __FreeBSD_kernel__ for the third case.) Submitted by: Andreas Tobler <andreast@fgznet.ch> (original version) Signed-off-by: Juergen Lock <nox@jelal.kn-bremen.de> Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc32: proper setcond implementationmalc2010-02-071-25/+25
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc32: implement setcond[2]malc2010-02-071-14/+157
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc: always use tcg_out_callmalc2009-09-271-20/+10
| | | | Signed-off-by: malc <av1474@comtv.ru>
* When targeting PPU use rlwinm instead of andi. if possiblemalc2009-09-061-8/+54
| | | | | | andi. is microcoded and slow there. Signed-off-by: malc <av1474@comtv.ru>
* Fix rbase initializationmalc2009-07-201-1/+1
| | | | Signed-off-by: malc <av1474@comtv.ru>
* PPC 32/64 GUEST_BASE supportmalc2009-07-182-21/+65
| | | | Signed-off-by: malc <av1474@comtv.ru>
* Fix LHZX opcode valuemalc2009-07-181-1/+1
| | | | Signed-off-by: malc <av1474@comtv.ru>
* Whack [LS]MWmalc2009-04-111-3/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
* Remove reserved registers from tcg_target_reg_alloc_ordermalc2009-04-111-3/+0
| | | | | | Noticed by Andreas Faerber git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7080 c046a42c-6fe2-441c-8c8c-71466251a162
* Prune unused TCG_AREGsblueswir12009-03-081-1/+0
| | | | | | | | | | Remove definitions for TCG_AREGs corresponding to AREG definitions removed in r6778. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
* Add missing r24..r26 to calle save registersmalc2009-02-111-0/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6612 c046a42c-6fe2-441c-8c8c-71466251a162
* R13 is reserved for small data area pointer by SVR4 PPC ABImalc2009-01-261-0/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6450 c046a42c-6fe2-441c-8c8c-71466251a162
* Use the ARRAY_SIZE() macro where appropriate.malc2008-12-221-1/+1
| | | | | | | | | Change from v1: Avoid changing the existing coding style in certain files. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
* Introduce and use cache-utils.[ch]malc2008-12-101-21/+0
| | | | | | | | | | | | Thanks to Segher Boessenkool and Holis Blanchard. AIX and Darwin cache inquiry: http://gcc.gnu.org/ml/gcc-patches/2007-08/msg00388.html Auxiliary vectors: http://manugarg.googlepages.com/aboutelfauxiliaryvectors git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5973 c046a42c-6fe2-441c-8c8c-71466251a162
* Preliminary AIX supportmalc2008-11-182-2/+52
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5732 c046a42c-6fe2-441c-8c8c-71466251a162
* Rename misnamed BACK_CHAIN_OFFSET to LR_OFFSETmalc2008-11-121-4/+4
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5711 c046a42c-6fe2-441c-8c8c-71466251a162
* Add some missing static and const qualifiers, reg_names only used if NDEBUG setblueswir12008-10-051-0/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
* Avoid clobbering input register in qemu_ld64+bswap+useronly casemalc2008-09-221-13/+6
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5287 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix some warnings that would be generated by gcc -Wredundant-declsblueswir12008-08-301-9/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
* Relax qemu_ld/st constraints for !SOFTMMU casemalc2008-08-211-1/+14
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5038 c046a42c-6fe2-441c-8c8c-71466251a162
* Account for MacOS X ABI reserved space in linkage area (Andreas Faerber)malc2008-08-032-2/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4985 c046a42c-6fe2-441c-8c8c-71466251a162
* Preliminary MacOS X on PPC32 supportmalc2008-08-032-10/+41
| | | | | | Big thanks to BlueSwirl for Sparc failure analysis. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4984 c046a42c-6fe2-441c-8c8c-71466251a162
* On ppc32 make tb_set_jmp_target1 behave like it does on a ppc64malc2008-07-291-0/+31
| | | | | | | | Avoids nasty warnings about flush_icache_range from gcc4 and inability to compile [cpu-]exec.c with gcc3 and -O, also the function is much too large to be candidate for inlining anyway. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4974 c046a42c-6fe2-441c-8c8c-71466251a162
* Do not try handle "special" arguments of and/or/xor/shl/shr, upper level does itmalc2008-07-281-64/+38
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4961 c046a42c-6fe2-441c-8c8c-71466251a162
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