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* TCG: Revert ppc64 tcg_out_movi32 changeAndreas Färber2010-08-151-1/+1
| | | | | | | | | | | | | 3b6dac34161bc0a342336072643c2f6d17e0ec45 apparently broke the ppc64 TCG target compilation in the code path without guest base. Reverting this line fixes the build. Signed-off-by: Andreas F?rber <andreas.faerber@web.de> Cc: malc <av1474@comtv.ru> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: malc <av1474@comtv.ru>
* tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.Richard Henderson2010-06-291-5/+4
| | | | | | | We need not reserve the register unless we're going to use it. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: malc <av1474@comtv.ru>
* tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.Richard Henderson2010-06-161-0/+1
| | | | | | | | | | | | | | | | | | Some hosts (amd64, ia64) have an ABI that ignores the high bits of the 64-bit register when passing 32-bit arguments. Others require the value to be properly sign-extended for the type. I.e. "int32_t" must be sign-extended and "uint32_t" must be zero-extended to 64-bits. To effect this, extend the "sizemask" parameter to tcg_gen_callN to include the signedness of the type of each parameter. If the tcg target requires it, extend each 32-bit argument into a 64-bit temp and pass that to the function call. This ABI feature is required by sparc64, ppc64 and s390x. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Make some tcg-target.c routines static.Richard Henderson2010-06-091-2/+2
| | | | | | | | Both tcg_target_init and tcg_target_qemu_prologue are unused outside of tcg.c. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Add TYPE parameter to tcg_out_mov.Richard Henderson2010-06-091-5/+5
| | | | | | | | | | | | | | Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64 to perform the move at the proper width, which may elide a REX prefix. Introduce a TCG_TYPE_REG enumerator to represent the "native width" of the host register, and to distinguish the usage from "pointer data" as represented by the existing TCG_TYPE_PTR. Update all targets to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/ppc64: Fix typomalc2010-04-071-1/+1
| | | | Signed-off-by: malc <av1474@comtv.ru>
* Split TLB addend and target_phys_addr_tPaul Brook2010-04-051-10/+2
| | | | | | | | | | | | | | Historically the qemu tlb "addend" field was used for both RAM and IO accesses, so needed to be able to hold both host addresses (unsigned long) and guest physical addresses (target_phys_addr_t). However since the introduction of the iotlb field it has only been used for RAM accesses. This means we can change the type of addend to unsigned long, and remove associated hacks in the big-endian TCG backends. We can also remove the host dependence from target_phys_addr_t. Signed-off-by: Paul Brook <paul@codesourcery.com>
* tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson2010-03-261-0/+2
| | | | | | | | | | | | | | | Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands sign-extended in 64-bit registers (regardless of the "real" sign of the operand). For that, we need to be able to distinguish between a 32-bit load with a 32-bit result and a 32-bit load with a given extension to a 64-bit result. This distinction already exists for the ld* loads, but not the qemu_ld* loads. Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for 32-bit outputs. Adjust all code generators to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of NOR.Richard Henderson2010-03-261-0/+2
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of NAND.Richard Henderson2010-03-261-0/+2
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of EQV.Richard Henderson2010-03-261-0/+2
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Use TCGCond where appropriate.Richard Henderson2010-03-261-3/+4
| | | | | | | | Use the TCGCond enumeration type in the brcond and setcond related prototypes in tcg-op.h and each code generator. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Name the opcode enumeration.Richard Henderson2010-03-261-1/+1
| | | | | | | | Give the enumeration formed from tcg-opc.h a name: TCGOpcode. Use that enumeration type instead of "int" whereever appropriate. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini2010-03-261-2/+0
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/ppc[64]: Only define addend load helpers in softmmu casemalc2010-03-131-0/+2
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc64: Use C90 style commentsmalc2010-02-221-18/+18
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg: Add comments for all optional instructions not implemented.Richard Henderson2010-02-201-3/+22
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg/ppc64: implement setcondmalc2010-02-071-0/+133
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc64: Fix loading of 32bit constantsmalc2009-12-151-1/+2
| | | | Signed-off-by: malc <av1474@comtv.ru>
* TCG: Mac OS X support for ppc64 targetAndreas Faerber2009-12-061-14/+41
| | | | | | | | | | | | | | | | | Darwin/ppc64 does not use function descriptors, adapt prologue and tcg_out_call accordingly. GPR2 is available for general use, so let's use it. http://developer.apple.com/mac/library/documentation/DeveloperTools/Conceptual/LowLevelABI/110-64-bit_PowerPC_Function_Calling_Conventions/64bitPowerPC.html v2: - Don't mark reserved GPR13 as callee-save. - Move tcg_out_b up. - Fix unused variable warning in prologue. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Cc: malc <av1474@comtv.ru> Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc64,x86_64: fix constraints of op_qemu_st64Aurelien Jarno2009-11-241-1/+1
| | | | | | This op only takes two arguments, not two. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* PPC 32/64 GUEST_BASE supportmalc2009-07-182-20/+62
| | | | Signed-off-by: malc <av1474@comtv.ru>
* Fix LHZX opcode valuemalc2009-07-181-1/+1
| | | | Signed-off-by: malc <av1474@comtv.ru>
* Remove reserved registers from tcg_target_reg_alloc_ordermalc2009-04-111-4/+0
| | | | | | Noticed by Andreas Faerber git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7082 c046a42c-6fe2-441c-8c8c-71466251a162
* Whack [LS]MWmalc2009-04-111-3/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
* Prune unused TCG_AREGsblueswir12009-03-081-1/+0
| | | | | | | | | | Remove definitions for TCG_AREGs corresponding to AREG definitions removed in r6778. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
* Add missing r24..r26 to callee save registersmalc2009-02-111-0/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6613 c046a42c-6fe2-441c-8c8c-71466251a162
* Use the ARRAY_SIZE() macro where appropriate.malc2008-12-221-1/+1
| | | | | | | | | Change from v1: Avoid changing the existing coding style in certain files. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
* Introduce and use cache-utils.[ch]malc2008-12-101-21/+0
| | | | | | | | | | | | Thanks to Segher Boessenkool and Holis Blanchard. AIX and Darwin cache inquiry: http://gcc.gnu.org/ml/gcc-patches/2007-08/msg00388.html Auxiliary vectors: http://manugarg.googlepages.com/aboutelfauxiliaryvectors git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5973 c046a42c-6fe2-441c-8c8c-71466251a162
* Avoid compiler warningmalc2008-11-121-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5710 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix alignment problem with some 64bit load/store instructionsmalc2008-11-111-5/+16
| | | | | | | | | LD/STD/LWA require displacement to be multiple of 4, provide tcg_out_ldsta which checks the supplied displacement and falls back on indexed variant when the check fails. All uses of LD/STD/LWA outside of tcg_out_ldst appear to be safe. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5670 c046a42c-6fe2-441c-8c8c-71466251a162
* Add some missing static and const qualifiers, reg_names only used if NDEBUG setblueswir12008-10-051-0/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
* Optimize 64 bit bswapmalc2008-10-021-5/+5
| | | | | | | Use rldimi instead of rldicr/or pair, saves us one instruction. Suggested by Hollis Blanchard. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5404 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix some warnings that would be generated by gcc -Wredundant-declsblueswir12008-08-301-9/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
* Relax qemu_ld/st constraints for !SOFTMMU casemalc2008-08-201-2/+6
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5034 c046a42c-6fe2-441c-8c8c-71466251a162
* Avoid clobbering input/aliased registers in !SOFTMMU+64bit+bswap casemalc2008-08-201-9/+10
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5033 c046a42c-6fe2-441c-8c8c-71466251a162
* Clear the upper 32 bits of addr_reg in TARGET_LONG_BITS == 32 casemalc2008-08-201-0/+6
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5032 c046a42c-6fe2-441c-8c8c-71466251a162
* Move tcg_out_tlb_read into #ifdef CONFIG_SOFTMMU block to avoid compiler warningmalc2008-08-201-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5031 c046a42c-6fe2-441c-8c8c-71466251a162
* Immediate versions of some operationsmalc2008-07-281-27/+57
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4962 c046a42c-6fe2-441c-8c8c-71466251a162
* Do not try handle "special" arguments of and/or/xor/shl/shr, upper level does itmalc2008-07-281-64/+38
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4961 c046a42c-6fe2-441c-8c8c-71466251a162
* Set the L field of CMP[L][I] when dealing with 64 bit quantitiesmalc2008-07-281-7/+12
| | | | | | This (along with previous 2 commits) makes X86_64 work on ppc64 too. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4960 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix preprocessor guard conditionmalc2008-07-281-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4959 c046a42c-6fe2-441c-8c8c-71466251a162
* Remove leftover from previous way to load 64 bit constantsmalc2008-07-281-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4958 c046a42c-6fe2-441c-8c8c-71466251a162
* Special-case some paths inside tcg_out_tlb_readmalc2008-07-271-6/+30
| | | | | | | a. Use 32bit arithmetics in TARGET_LONG_BITS == 32 case b. Optimize byte access case in TARGET_LONG_BITS == 64 case git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4955 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix the opcode value of LWAmalc2008-07-271-1/+1
| | | | | | | | | | That should teach one to not blindly trust documentation that will (out of the blue) use decimal and binary representation for numbers in the same chart for no apparent reason and without any prefixes, sigh.. Unbreaks MIPS. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4954 c046a42c-6fe2-441c-8c8c-71466251a162
* Relax memory operations constraintsmalc2008-07-261-17/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4950 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix qemu_ld64 constraint listmalc2008-07-261-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4949 c046a42c-6fe2-441c-8c8c-71466251a162
* Use proper offset for LR save slotmalc2008-07-261-2/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4948 c046a42c-6fe2-441c-8c8c-71466251a162
* Reduce amount of space reserved for tb jumpmalc2008-07-261-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4947 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix and improve 64 bit immediate loadingmalc2008-07-261-4/+7
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4946 c046a42c-6fe2-441c-8c8c-71466251a162
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