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* tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.hStefan Weil2011-10-011-1/+0
* tcg/ppc64: Only one call output register needed for 64 bit hostsStefan Weil2011-09-171-1/+1
* tcg/ppc64: Fix zero extension code generation bug for ppc64 hostThomas Huth2011-09-091-1/+1
* tcg/ppc64: fix 16/32 mixupmalc2011-08-221-2/+2
* tcg/ppc64: implement not_i32/64 and ext32u_i64malc2011-08-222-3/+16
* tcg: Always define all of the TCGOpcode enum members.Richard Henderson2011-08-211-33/+35
* TCG/PPC: use stack for TCG tempsBlue Swirl2011-06-281-2/+5
* tcg/ppc64: Remove tcg_out_addimalc2011-06-281-5/+0
* Delegate setup of TCG temporaries to targetsBlue Swirl2011-06-261-0/+2
* cpu-exec.c: avoid AREG0 useBlue Swirl2011-06-261-3/+3
* TCG: Revert ppc64 tcg_out_movi32 changeAndreas Färber2010-08-151-1/+1
* tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.Richard Henderson2010-06-291-5/+4
* tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.Richard Henderson2010-06-161-0/+1
* tcg: Make some tcg-target.c routines static.Richard Henderson2010-06-091-2/+2
* tcg: Add TYPE parameter to tcg_out_mov.Richard Henderson2010-06-091-5/+5
* tcg/ppc64: Fix typomalc2010-04-071-1/+1
* Split TLB addend and target_phys_addr_tPaul Brook2010-04-051-10/+2
* tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson2010-03-261-0/+2
* tcg: Allow target-specific implementation of NOR.Richard Henderson2010-03-261-0/+2
* tcg: Allow target-specific implementation of NAND.Richard Henderson2010-03-261-0/+2
* tcg: Allow target-specific implementation of EQV.Richard Henderson2010-03-261-0/+2
* tcg: Use TCGCond where appropriate.Richard Henderson2010-03-261-3/+4
* tcg: Name the opcode enumeration.Richard Henderson2010-03-261-1/+1
* remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini2010-03-261-2/+0
* tcg/ppc[64]: Only define addend load helpers in softmmu casemalc2010-03-131-0/+2
* tcg/ppc64: Use C90 style commentsmalc2010-02-221-18/+18
* tcg: Add comments for all optional instructions not implemented.Richard Henderson2010-02-201-3/+22
* tcg/ppc64: implement setcondmalc2010-02-071-0/+133
* tcg/ppc64: Fix loading of 32bit constantsmalc2009-12-151-1/+2
* TCG: Mac OS X support for ppc64 targetAndreas Faerber2009-12-061-14/+41
* tcg/ppc64,x86_64: fix constraints of op_qemu_st64Aurelien Jarno2009-11-241-1/+1
* PPC 32/64 GUEST_BASE supportmalc2009-07-182-20/+62
* Fix LHZX opcode valuemalc2009-07-181-1/+1
* Remove reserved registers from tcg_target_reg_alloc_ordermalc2009-04-111-4/+0
* Whack [LS]MWmalc2009-04-111-3/+0
* Prune unused TCG_AREGsblueswir12009-03-081-1/+0
* Add missing r24..r26 to callee save registersmalc2009-02-111-0/+5
* Use the ARRAY_SIZE() macro where appropriate.malc2008-12-221-1/+1
* Introduce and use cache-utils.[ch]malc2008-12-101-21/+0
* Avoid compiler warningmalc2008-11-121-1/+1
* Fix alignment problem with some 64bit load/store instructionsmalc2008-11-111-5/+16
* Add some missing static and const qualifiers, reg_names only used if NDEBUG setblueswir12008-10-051-0/+2
* Optimize 64 bit bswapmalc2008-10-021-5/+5
* Fix some warnings that would be generated by gcc -Wredundant-declsblueswir12008-08-301-9/+2
* Relax qemu_ld/st constraints for !SOFTMMU casemalc2008-08-201-2/+6
* Avoid clobbering input/aliased registers in !SOFTMMU+64bit+bswap casemalc2008-08-201-9/+10
* Clear the upper 32 bits of addr_reg in TARGET_LONG_BITS == 32 casemalc2008-08-201-0/+6
* Move tcg_out_tlb_read into #ifdef CONFIG_SOFTMMU block to avoid compiler warningmalc2008-08-201-1/+1
* Immediate versions of some operationsmalc2008-07-281-27/+57
* Do not try handle "special" arguments of and/or/xor/shl/shr, upper level does itmalc2008-07-281-64/+38
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