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* Restore consistent formattingmalc2012-05-031-18/+18
| | | | Signed-off-by: malc <av1474@comtv.ru>
* qemu tcg: Remove one entry of INDEX_op_ld_i64 from ppc_op_defsLi Zhang2012-03-291-1/+0
| | | | | | | | | | There two entries of INDEX_op_ld_i64 in the ppc_op_defs. That causes an assertion failure in tcg_add_target_add_op_defs() when --enable-debug is used on a ppc64 backend (that's ppc64 host, not target). Signed-off-by: Li Zhang <zhlcindy@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: malc <av1474@comtv.ru>
* softmmu templates: optionally pass CPUState to memory access functionsBlue Swirl2012-03-181-0/+44
| | | | | | | | | | | Optionally, make memory access helpers take a parameter for CPUState instead of relying on global env. On most targets, perform simple moves to reorder registers. On i386, switch from regparm(3) calling convention to standard stack-based version. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Rename CPUState -> CPUArchStateAndreas Färber2012-03-141-2/+2
| | | | | | | | | | | | | Scripted conversion: for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done All occurrences of CPUArchState are expected to be replaced by QOM CPUState, once all targets are QOM'ified and common fields have been extracted. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
* Merge branch 's390-1.0' of git://repo.or.cz/qemu/agrafBlue Swirl2011-11-192-6/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 's390-1.0' of git://repo.or.cz/qemu/agraf: s390x: initialize virtio dev region tcg: Use TCGReg for standard tcg-target entry points. tcg: Standardize on TCGReg as the enum for hard registers s390x: Add shutdown for TCG s390-virtio machine s390: Fix cpu shutdown for KVM s390: fix short kernel command lines s390: fix reset hypercall to reset the status s390x: implement SIGP restart and shutdown s390x: implement rrbe instruction properly s390x: update R and C bits in storage key s390x: make ipte 31-bit aware s390x: add ldeb instruction
| * tcg: Use TCGReg for standard tcg-target entry points.Richard Henderson2011-11-141-4/+4
| | | | | | | | | | | | | | | | | | Including tcg_out_ld, tcg_out_st, tcg_out_mov, tcg_out_movi. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de>
| * tcg: Standardize on TCGReg as the enum for hard registersRichard Henderson2011-11-141-2/+2
| | | | | | | | | | | | | | | | | | Most targets did not name the enum; tci used TCGRegister. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* | tcg-ppc64: Fix compile errors for userspace only builds with gcc 4.6David Gibson2011-11-111-6/+8
|/ | | | | | | | | | | | tcg/ppc64/tcg-target.c has a couple of places where variables are set unconditionally, but otherwise used only for softmmu builds, not userspace only builds. This causes compiler warnings (which are fatal by default) when compiling for a ppc64 host with gcc 4.6. This patch fixes the problem by moving the code which defines and sets the variables into the CONFIG_SOFTMMU guarded regions. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.hStefan Weil2011-10-011-1/+0
| | | | | | | | It is now declared for all tcg targets in tcg.h, so the tcg target specific declarations are redundant. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg/ppc64: Only one call output register needed for 64 bit hostsStefan Weil2011-09-171-1/+1
| | | | | | | | | The second register is only needed for 32 bit hosts. Cc: Vassili Karpov <av1474@comtv.ru> Fine-with-me'd-by: Vassili Karpov <av1474@comtv.ru> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg/ppc64: Fix zero extension code generation bug for ppc64 hostThomas Huth2011-09-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | The ppc64 code generation backend uses an rldicr (Rotate Left Double Immediate and Clear Right) instruction to implement zero extension of a 32 bit quantity to a 64 bit quantity (INDEX_op_ext32u_i64). However this is wrong - this instruction clears specified low bits of the value, instead of high bits as we require for a zero extension. It should instead use an rldicl (Rotate Left Double Immediate and Clear Left) instruction. Presumably amongst other things, this causes the SLOF firmware image used with -M pseries to not boot on a ppc64 host. It appears this bug was exposed by commit 0bf1dbdcc935dfc220a93cd990e947e90706aec6 (tcg/ppc64: fix 16/32 mixup) which enabled the use of the op_ext32u_i64 operation on the ppc64 backend. Signed-off-by: Thomas Huth <thuth@de.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc64: fix 16/32 mixupmalc2011-08-221-2/+2
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc64: implement not_i32/64 and ext32u_i64malc2011-08-222-3/+16
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg: Always define all of the TCGOpcode enum members.Richard Henderson2011-08-211-33/+35
| | | | | | | | | | | | By always defining these symbols, we can eliminate a lot of ifdefs. To allow this to be checked reliably, the semantics of the TCG_TARGET_HAS_* macros must be changed from def/undef to true/false. This allows even more ifdefs to be removed, converting them into C if statements. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* TCG/PPC: use stack for TCG tempsBlue Swirl2011-06-281-2/+5
| | | | | | | Use stack instead of temp_buf array in CPUState for TCG temps. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc64: Remove tcg_out_addimalc2011-06-281-5/+0
| | | | | | The only user (within tcg.c) was removed Signed-off-by: malc <av1474@comtv.ru>
* Delegate setup of TCG temporaries to targetsBlue Swirl2011-06-261-0/+2
| | | | | | | Delegate TCG temp_buf setup to targets, so that they can use a stack frame later instead. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* cpu-exec.c: avoid AREG0 useBlue Swirl2011-06-261-3/+3
| | | | | | | | | | | | | | | | | Make functions take a parameter for CPUState instead of relying on global env. Pass CPUState pointer to TCG prologue, which moves it to AREG0. Thanks to Peter Maydell and Laurent Desnogues for the ARM prologue change. Revert the hacks to avoid AREG0 use on Sparc hosts. Move cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. Compile the file without HELPER_CFLAGS. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* TCG: Revert ppc64 tcg_out_movi32 changeAndreas Färber2010-08-151-1/+1
| | | | | | | | | | | | | 3b6dac34161bc0a342336072643c2f6d17e0ec45 apparently broke the ppc64 TCG target compilation in the code path without guest base. Reverting this line fixes the build. Signed-off-by: Andreas F?rber <andreas.faerber@web.de> Cc: malc <av1474@comtv.ru> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: malc <av1474@comtv.ru>
* tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.Richard Henderson2010-06-291-5/+4
| | | | | | | We need not reserve the register unless we're going to use it. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: malc <av1474@comtv.ru>
* tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.Richard Henderson2010-06-161-0/+1
| | | | | | | | | | | | | | | | | | Some hosts (amd64, ia64) have an ABI that ignores the high bits of the 64-bit register when passing 32-bit arguments. Others require the value to be properly sign-extended for the type. I.e. "int32_t" must be sign-extended and "uint32_t" must be zero-extended to 64-bits. To effect this, extend the "sizemask" parameter to tcg_gen_callN to include the signedness of the type of each parameter. If the tcg target requires it, extend each 32-bit argument into a 64-bit temp and pass that to the function call. This ABI feature is required by sparc64, ppc64 and s390x. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Make some tcg-target.c routines static.Richard Henderson2010-06-091-2/+2
| | | | | | | | Both tcg_target_init and tcg_target_qemu_prologue are unused outside of tcg.c. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Add TYPE parameter to tcg_out_mov.Richard Henderson2010-06-091-5/+5
| | | | | | | | | | | | | | Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64 to perform the move at the proper width, which may elide a REX prefix. Introduce a TCG_TYPE_REG enumerator to represent the "native width" of the host register, and to distinguish the usage from "pointer data" as represented by the existing TCG_TYPE_PTR. Update all targets to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/ppc64: Fix typomalc2010-04-071-1/+1
| | | | Signed-off-by: malc <av1474@comtv.ru>
* Split TLB addend and target_phys_addr_tPaul Brook2010-04-051-10/+2
| | | | | | | | | | | | | | Historically the qemu tlb "addend" field was used for both RAM and IO accesses, so needed to be able to hold both host addresses (unsigned long) and guest physical addresses (target_phys_addr_t). However since the introduction of the iotlb field it has only been used for RAM accesses. This means we can change the type of addend to unsigned long, and remove associated hacks in the big-endian TCG backends. We can also remove the host dependence from target_phys_addr_t. Signed-off-by: Paul Brook <paul@codesourcery.com>
* tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson2010-03-261-0/+2
| | | | | | | | | | | | | | | Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands sign-extended in 64-bit registers (regardless of the "real" sign of the operand). For that, we need to be able to distinguish between a 32-bit load with a 32-bit result and a 32-bit load with a given extension to a 64-bit result. This distinction already exists for the ld* loads, but not the qemu_ld* loads. Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for 32-bit outputs. Adjust all code generators to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of NOR.Richard Henderson2010-03-261-0/+2
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of NAND.Richard Henderson2010-03-261-0/+2
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of EQV.Richard Henderson2010-03-261-0/+2
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Use TCGCond where appropriate.Richard Henderson2010-03-261-3/+4
| | | | | | | | Use the TCGCond enumeration type in the brcond and setcond related prototypes in tcg-op.h and each code generator. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Name the opcode enumeration.Richard Henderson2010-03-261-1/+1
| | | | | | | | Give the enumeration formed from tcg-opc.h a name: TCGOpcode. Use that enumeration type instead of "int" whereever appropriate. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini2010-03-261-2/+0
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/ppc[64]: Only define addend load helpers in softmmu casemalc2010-03-131-0/+2
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc64: Use C90 style commentsmalc2010-02-221-18/+18
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg: Add comments for all optional instructions not implemented.Richard Henderson2010-02-201-3/+22
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg/ppc64: implement setcondmalc2010-02-071-0/+133
| | | | Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc64: Fix loading of 32bit constantsmalc2009-12-151-1/+2
| | | | Signed-off-by: malc <av1474@comtv.ru>
* TCG: Mac OS X support for ppc64 targetAndreas Faerber2009-12-061-14/+41
| | | | | | | | | | | | | | | | | Darwin/ppc64 does not use function descriptors, adapt prologue and tcg_out_call accordingly. GPR2 is available for general use, so let's use it. http://developer.apple.com/mac/library/documentation/DeveloperTools/Conceptual/LowLevelABI/110-64-bit_PowerPC_Function_Calling_Conventions/64bitPowerPC.html v2: - Don't mark reserved GPR13 as callee-save. - Move tcg_out_b up. - Fix unused variable warning in prologue. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Cc: malc <av1474@comtv.ru> Signed-off-by: malc <av1474@comtv.ru>
* tcg/ppc64,x86_64: fix constraints of op_qemu_st64Aurelien Jarno2009-11-241-1/+1
| | | | | | This op only takes two arguments, not two. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* PPC 32/64 GUEST_BASE supportmalc2009-07-182-20/+62
| | | | Signed-off-by: malc <av1474@comtv.ru>
* Fix LHZX opcode valuemalc2009-07-181-1/+1
| | | | Signed-off-by: malc <av1474@comtv.ru>
* Remove reserved registers from tcg_target_reg_alloc_ordermalc2009-04-111-4/+0
| | | | | | Noticed by Andreas Faerber git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7082 c046a42c-6fe2-441c-8c8c-71466251a162
* Whack [LS]MWmalc2009-04-111-3/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
* Prune unused TCG_AREGsblueswir12009-03-081-1/+0
| | | | | | | | | | Remove definitions for TCG_AREGs corresponding to AREG definitions removed in r6778. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
* Add missing r24..r26 to callee save registersmalc2009-02-111-0/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6613 c046a42c-6fe2-441c-8c8c-71466251a162
* Use the ARRAY_SIZE() macro where appropriate.malc2008-12-221-1/+1
| | | | | | | | | Change from v1: Avoid changing the existing coding style in certain files. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
* Introduce and use cache-utils.[ch]malc2008-12-101-21/+0
| | | | | | | | | | | | Thanks to Segher Boessenkool and Holis Blanchard. AIX and Darwin cache inquiry: http://gcc.gnu.org/ml/gcc-patches/2007-08/msg00388.html Auxiliary vectors: http://manugarg.googlepages.com/aboutelfauxiliaryvectors git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5973 c046a42c-6fe2-441c-8c8c-71466251a162
* Avoid compiler warningmalc2008-11-121-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5710 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix alignment problem with some 64bit load/store instructionsmalc2008-11-111-5/+16
| | | | | | | | | LD/STD/LWA require displacement to be multiple of 4, provide tcg_out_ldsta which checks the supplied displacement and falls back on indexed variant when the check fails. All uses of LD/STD/LWA outside of tcg_out_ldst appear to be safe. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5670 c046a42c-6fe2-441c-8c8c-71466251a162
* Add some missing static and const qualifiers, reg_names only used if NDEBUG setblueswir12008-10-051-0/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
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