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* tcg/arm: don't save/restore r7 in prologue/epilogueAurelien Jarno2010-03-201-6/+6
| | | | | | | There is no need to save r7, it is used to store the address of the env structure and is not modified by GCC. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: fix load/store definitions for 32-bit targetsAurelien Jarno2010-03-201-0/+14
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: use helpers for divu/remuAurelien Jarno2010-03-142-95/+0
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: add div/rem 32-bit helpersAurelien Jarno2010-03-141-0/+1
| | | | | | | | | | | Some targets like ARM would benefit to use 32-bit helpers for div/rem/divu/remu. Create a #define for div2 so that targets can select between div, div2 and helper implementation. Use the helper version if none of the #define are present. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: implement andc opAurelien Jarno2010-03-132-1/+5
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: correctly save/restore registers in prologue/epilogueAurelien Jarno2010-03-131-4/+7
| | | | | | | | | | | | | | | | | | | | Since commit 6113d6d3169393c323ac4c82d756a850145a5e7a QEMU crashes on ARM hosts. This is not a bug of this commit, but a latent bug revealed by this commit. The TCG code is called through a procedure call using the prologue and epilogue code. This code does not save and restore enough registers. The "Procedure Call Standard for the ARM Architecture" says: A subroutine must preserve the contents of the registers r4-r8, r10,  r11 and SP (and r9 in PCS variants that designate r9 as v6). The current code only saves and restores r9 to r11, and misses r4 to r8. The patch fixes that by saving r4 to r12. Theoretically there is no need to save and restore r12, but an even number of registers have to be saved as per EABI. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Remove TLB from userspacePaul Brook2010-03-121-0/+2
| | | | | | Remove TLB from userspace CPU structure. Signed-off-by: Paul Brook <paul@codesourcery.com>
* tcg/arm: merge the two sets of #define for optional opsAurelien Jarno2010-03-021-14/+5
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/arm: accept immediate arguments for brcond/setcondAurelien Jarno2010-03-021-6/+20
| | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* Add a missing breakAndrzej Zaborowski2010-03-021-0/+1
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* tcg/arm: implement setcond2Aurelien Jarno2010-03-021-0/+11
| | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* tcg/arm: implement setcondAurelien Jarno2010-03-021-0/+9
| | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* tcg/arm: fix div2/divu2Aurelien Jarno2010-03-021-6/+24
| | | | | | | | When restoring register values, increase the stack register for skipped values. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* tcg: Add comments for all optional instructions not implemented.Richard Henderson2010-02-201-0/+14
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* ARM back-end: Use sxt[bh] instructions for ext{8, 6}sLaurent Desnogues2009-09-261-0/+10
| | | | | | | This patch uses sxtb for ext8s_i32 and sxth for ext16s_i32 in ARM back-end. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Suppress some variants of English in commentsStefan Weil2009-09-251-2/+2
| | | | | | | Replace surpress, supress by suppress. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* ARM back-end: Fix encode_immLaurent Desnogues2009-08-251-0/+2
| | | | | | | | | the encode_imm function in tcg/arm/tcg-target.c lacks shift declaration. Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* ARM back-end: Handle all possible immediates for ALU opsLaurent Desnogues2009-08-221-5/+32
| | | | | | | | | | this patch handles all possible constants for immediate operand of ALU ops. I'm not very satisfied by the implementation. Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* ARM back-end: Add TCG notLaurent Desnogues2009-08-222-0/+6
| | | | | | | | | | | this patch: - implements TCG not. Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIANJuan Quintela2009-07-271-1/+1
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* this patch improves the ARM back-end in the following way:Laurent Desnogues2009-07-182-7/+37
| | | | | | | | | | - use movw/movt to load immediate values for ARMv7-A - implement add/sub/and/or/xor with immediate (only 8-bit) Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* Userspace guest address offsettingPaul Brook2009-07-172-2/+34
| | | | | | | | | | Re-implement GUEST_BASE support. Offset guest ddress space by default if the guest binary contains regions below the host mmap_min_addr. Implement support for i386, x86-64 and arm hosts. Signed-off-by: Riku Voipio <riku.voipio@iki.fi> Signed-off-by: Paul Brook <paul@codesourcery.com>
* ARM host fixesPaul Brook2009-07-172-4/+4
| | | | | | Minor TCG cleanups and warning fixes for ARM hosts. Signed-off-by: Paul Brook <paul@codesourcery.com>
* tcg: rename bswap_i32/i64 functionsaurel322009-03-131-1/+1
| | | | | | | | Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg-arm: fix qemu_ld64aurel322009-03-101-2/+7
| | | | | | | | | | | | | | | Emulating fldl on arm doesn't seem to work too well. It's the way qemu_ld64 is translated to arm instructions. tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0); tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4); Consider case where data_reg==0, data_reg2==1, and addr_reg==0. First load overwrited addr_reg. So let's put an if (data_ref==addr_reg). (Pablo Virolainen) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6808 c046a42c-6fe2-441c-8c8c-71466251a162
* Prune unused TCG_AREGsblueswir12009-03-081-1/+0
| | | | | | | | | | Remove definitions for TCG_AREGs corresponding to AREG definitions removed in r6778. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix 64-bit targets compilation on ARM host.balrog2008-12-071-6/+6
| | | | | | | Only fix compilation, probably doesn't run. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5947 c046a42c-6fe2-441c-8c8c-71466251a162
* arm: Don't potentially overwrite input registers in add2, sub2.balrog2008-12-011-4/+13
| | | | | | | | | According to malc TCG will often genereate an add2/sub2/mul2 with low half of the output in the same register as high half of one of the inputs, so account for that. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5847 c046a42c-6fe2-441c-8c8c-71466251a162
* Don't rely on ARM tcg_out_goto() generating just a single insn.balrog2008-12-011-8/+13
| | | | | | | | | | | Otherwise when tb_exit generates a jump beyond the pc-relative range, tcg_out_goto() spans two/three instructions and we load the tb return value from a wrong address. This is #ifdefed out currently because we take care for the jumps to be local. Problem spotted by Steffen Liebergeld. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5845 c046a42c-6fe2-441c-8c8c-71466251a162
* Use libgcc __clear_cache to clean icache, when available.balrog2008-12-011-0/+5
| | | | | | | | Calling the clear cache syscall directly generates an illegal instruction on some (armv4) kernels. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5843 c046a42c-6fe2-441c-8c8c-71466251a162
* Add some missing static and const qualifiers, reg_names only used if NDEBUG setblueswir12008-10-051-5/+8
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix some warnings that would be generated by gcc -Wredundant-declsblueswir12008-08-301-9/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix off-by-one unwinding error.pbrook2008-05-251-1/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
* Relax a constraint for qemu_ld64 on ARM host.balrog2008-05-241-4/+13
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4567 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix a deadly typo, correct comments.balrog2008-05-241-4/+6
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4566 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix ARM host TLB.pbrook2008-05-241-61/+44
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4564 c046a42c-6fe2-441c-8c8c-71466251a162
* Comment non-obvious calculation. Don't clobber r3 in qemu_st64.balrog2008-05-231-6/+33
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4548 c046a42c-6fe2-441c-8c8c-71466251a162
* A branch insn must not overwrite the branch target before relocation.balrog2008-05-231-3/+14
| | | | | | | | | | | | | When a branch to label is translated it generates a reloc that is filled in when the label is translated. However, when handling an exception and searching for the pc we abort the translation early and we sometimes translate the branch but not the corresponding label and so no relocation is done. When the block is executed again the branch points to no-where. It seems tcg/sparc/ is going to suffer from the same issue. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4547 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix qemu_ld/st for mem_index > 0 on arm host.balrog2008-05-231-6/+15
| | | | | | | | | offsetof(CPUState, tlb_table[mem_index][0].addr_read) with mem_index > 0 was larger than max immediate offset for ldr and str (12-bit) so insert an additional insn to add the mem_index offset. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4542 c046a42c-6fe2-441c-8c8c-71466251a162
* Define TCG_TARGET_CALL_STACK_OFFSET on arm.balrog2008-05-231-2/+3
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4541 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix 8-bit signed load/store and a typo.balrog2008-05-201-4/+4
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4504 c046a42c-6fe2-441c-8c8c-71466251a162
* Implement neg_i32, clean-up.balrog2008-05-202-5/+10
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4503 c046a42c-6fe2-441c-8c8c-71466251a162
* ARM host support for TCG targets.balrog2008-05-192-0/+1621
Updated from previous version to use the tcg prologue/epilogue mechanism, may be slower than direct call. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4500 c046a42c-6fe2-441c-8c8c-71466251a162
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