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* tcg/arm: Replace qemu_ld32u (left over from previous commit)Stefan Weil2010-03-281-1/+1
* tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson2010-03-261-2/+2
* tcg: Allow target-specific implementation of NOR.Richard Henderson2010-03-261-0/+1
* tcg: Allow target-specific implementation of NAND.Richard Henderson2010-03-261-0/+1
* tcg: Allow target-specific implementation of EQV.Richard Henderson2010-03-261-0/+1
* tcg: Name the opcode enumeration.Richard Henderson2010-03-261-1/+1
* remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini2010-03-261-2/+0
* tcg/arm: don't save/restore r7 in prologue/epilogueAurelien Jarno2010-03-201-6/+6
* tcg/arm: fix load/store definitions for 32-bit targetsAurelien Jarno2010-03-201-0/+14
* tcg/arm: use helpers for divu/remuAurelien Jarno2010-03-142-95/+0
* tcg: add div/rem 32-bit helpersAurelien Jarno2010-03-141-0/+1
* tcg/arm: implement andc opAurelien Jarno2010-03-132-1/+5
* tcg/arm: correctly save/restore registers in prologue/epilogueAurelien Jarno2010-03-131-4/+7
* Remove TLB from userspacePaul Brook2010-03-121-0/+2
* tcg/arm: merge the two sets of #define for optional opsAurelien Jarno2010-03-021-14/+5
* tcg/arm: accept immediate arguments for brcond/setcondAurelien Jarno2010-03-021-6/+20
* Add a missing breakAndrzej Zaborowski2010-03-021-0/+1
* tcg/arm: implement setcond2Aurelien Jarno2010-03-021-0/+11
* tcg/arm: implement setcondAurelien Jarno2010-03-021-0/+9
* tcg/arm: fix div2/divu2Aurelien Jarno2010-03-021-6/+24
* tcg: Add comments for all optional instructions not implemented.Richard Henderson2010-02-201-0/+14
* ARM back-end: Use sxt[bh] instructions for ext{8, 6}sLaurent Desnogues2009-09-261-0/+10
* Suppress some variants of English in commentsStefan Weil2009-09-251-2/+2
* ARM back-end: Fix encode_immLaurent Desnogues2009-08-251-0/+2
* ARM back-end: Handle all possible immediates for ALU opsLaurent Desnogues2009-08-221-5/+32
* ARM back-end: Add TCG notLaurent Desnogues2009-08-222-0/+6
* rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIANJuan Quintela2009-07-271-1/+1
* this patch improves the ARM back-end in the following way:Laurent Desnogues2009-07-182-7/+37
* Userspace guest address offsettingPaul Brook2009-07-172-2/+34
* ARM host fixesPaul Brook2009-07-172-4/+4
* tcg: rename bswap_i32/i64 functionsaurel322009-03-131-1/+1
* tcg-arm: fix qemu_ld64aurel322009-03-101-2/+7
* Prune unused TCG_AREGsblueswir12009-03-081-1/+0
* Fix 64-bit targets compilation on ARM host.balrog2008-12-071-6/+6
* arm: Don't potentially overwrite input registers in add2, sub2.balrog2008-12-011-4/+13
* Don't rely on ARM tcg_out_goto() generating just a single insn.balrog2008-12-011-8/+13
* Use libgcc __clear_cache to clean icache, when available.balrog2008-12-011-0/+5
* Add some missing static and const qualifiers, reg_names only used if NDEBUG setblueswir12008-10-051-5/+8
* Fix some warnings that would be generated by gcc -Wredundant-declsblueswir12008-08-301-9/+2
* Fix off-by-one unwinding error.pbrook2008-05-251-1/+0
* Relax a constraint for qemu_ld64 on ARM host.balrog2008-05-241-4/+13
* Fix a deadly typo, correct comments.balrog2008-05-241-4/+6
* Fix ARM host TLB.pbrook2008-05-241-61/+44
* Comment non-obvious calculation. Don't clobber r3 in qemu_st64.balrog2008-05-231-6/+33
* A branch insn must not overwrite the branch target before relocation.balrog2008-05-231-3/+14
* Fix qemu_ld/st for mem_index > 0 on arm host.balrog2008-05-231-6/+15
* Define TCG_TARGET_CALL_STACK_OFFSET on arm.balrog2008-05-231-2/+3
* Fix 8-bit signed load/store and a typo.balrog2008-05-201-4/+4
* Implement neg_i32, clean-up.balrog2008-05-202-5/+10
* ARM host support for TCG targets.balrog2008-05-192-0/+1621
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