summaryrefslogtreecommitdiffstats
path: root/target-xtensa
Commit message (Expand)AuthorAgeFilesLines
* gen-icount: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-1/+1
* target-xtensa: don't generate dead codeMax Filippov2014-12-171-279/+321
* target-xtensa: record available window in TB flagsMax Filippov2014-12-174-62/+42
* target-xtensa: fix translation for opcodes crossing page boundaryMax Filippov2014-12-171-4/+23
* target-xtensa: add missing window check for entryMax Filippov2014-11-102-0/+12
* Merge remote-tracking branch 'remotes/xtensa/tags/20141103-xtensa' into stagingPeter Maydell2014-11-033-12/+74
|\
| * target-xtensa: fix build for cores w/o windowed registersMax Filippov2014-11-031-12/+19
| * target-xtensa: add core importing scriptMax Filippov2014-11-031-0/+53
| * target-xtensa: add definition for XTHAL_INTTYPE_PROFILINGMax Filippov2014-11-032-0/+2
* | target-xtensa: mark XtensaConfig structs as unusedPeter Maydell2014-11-023-3/+3
|/
* gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flagPeter Maydell2014-10-061-0/+1
* target-xtensa: Use cpu_exec_interrupt qom hookRichard Henderson2014-09-253-0/+12
* cpu-exec: Make debug_excp_handler a QOM CPU methodPeter Maydell2014-09-123-4/+5
* trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova2014-08-121-0/+3
* softmmu: introduce cpu_ldst.hPaolo Bonzini2014-06-052-1/+2
* softmmu: commonize helper definitionsPaolo Bonzini2014-06-051-14/+1
* softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini2014-06-052-1/+1
* softmmu: make do_unaligned_access a method of CPUPaolo Bonzini2014-06-053-6/+7
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-284-9/+4
* target-xtensa: fix cross-page jumps/calls at the end of TBMax Filippov2014-05-261-2/+2
* cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber2014-03-131-4/+4
* cputlb: Change tlb_flush() argument to CPUStateAndreas Färber2014-03-131-1/+3
* cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber2014-03-131-4/+6
* cpu-exec: Change cpu_resume_from_signal() argument to CPUStateAndreas Färber2014-03-131-1/+1
* exec: Change cpu_watchpoint_{insert,remove{,_by_ref,_all}} argumentAndreas Färber2014-03-131-3/+6
* translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber2014-03-131-2/+4
* cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber2014-03-131-2/+2
* exec: Change tlb_fill() argument to CPUStateAndreas Färber2014-03-131-2/+4
* cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-2/+3
* cpu: Move watchpoint fields from CPU_COMMON to CPUStateAndreas Färber2014-03-132-4/+6
* cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber2014-03-132-10/+14
* cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2014-03-132-7/+8
* target-xtensa: Clean up ENV_GET_CPU() usageAndreas Färber2014-03-132-2/+4
* target-xtensa: provide HW confg ID registersMax Filippov2014-02-244-3/+21
* target-xtensa: refactor standard core configurationMax Filippov2014-02-244-21/+13
* target-xtensa: add basic checks to icache opcodesMax Filippov2014-02-243-0/+33
* target-xtensa: add basic checks to dcache opcodesMax Filippov2014-02-241-0/+38
* target-xtensa: add RRRI4 opcode format fieldsMax Filippov2014-02-241-0/+9
* exec: Make ldl_*_phys input an AddressSpaceEdgar E. Iglesias2014-02-111-1/+2
* exec: Make tb_invalidate_phys_addr input an ASEdgar E. Iglesias2014-02-111-1/+2
* target-xtensa: add missing DEBUG section to dc233c configMax Filippov2013-11-081-0/+1
* target-xtensa: add in_asm loggingMax Filippov2013-10-151-0/+8
* tcg: Move helper registration into tcg_context_initRichard Henderson2013-10-101-2/+0
* target: Include softmmu_exec.h where forgottenRichard Henderson2013-09-021-0/+1
* tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson2013-09-021-1/+1
* aio / timers: Switch entire codebase to the new timer APIAlex Bligh2013-08-221-1/+1
* Merge remote-tracking branch 'filippov/tags/20130729-xtensa' into stagingAnthony Liguori2013-08-053-23/+53
|\
| * target-xtensa: check register window inlineMax Filippov2013-07-291-8/+25
| * target-xtensa: don't generate dead code to access invalid SRsMax Filippov2013-07-291-13/+18
| * target-xtensa: avoid double-stopping at breakpointsMax Filippov2013-07-293-2/+8
OpenPOWER on IntegriCloud