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* Rename cpu_reset() to cpu_state_reset()Andreas Färber2012-03-141-1/+1
* Merge branch 'upstream' of git://qemu.weilnetz.de/qemuBlue Swirl2012-03-033-3/+0
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| * target-xtensa: Clean includesStefan Weil2012-02-283-3/+0
* | target-xtensa: add DEBUG_SECTION to overlay toolMax Filippov2012-02-203-0/+7
* | target-xtensa: add DBREAK data breakpointsMax Filippov2012-02-205-0/+147
* | target-xtensa: add ICOUNT SR and debug exceptionMax Filippov2012-02-182-1/+54
* | target-xtensa: implement instruction breakpointsMax Filippov2012-02-185-3/+119
* | target-xtensa: add DEBUGCAUSE SR and configurationMax Filippov2012-02-182-0/+21
* | target-xtensa: fetch 3rd opcode byte only when neededMax Filippov2012-02-181-1/+2
* | target-xtensa: implement info tlb monitor commandMax Filippov2012-02-182-0/+68
* | target-xtensa: define TLB_TEMPLATE for MMU-less coresMax Filippov2012-02-181-2/+16
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* target-xtensa: fix MMUv3 initializationMax Filippov2011-11-262-2/+2
* target-xtensa: raise an exception for invalid and reserved opcodesMax Filippov2011-11-021-1/+6
* target-xtensa: handle cache options in the overlay toolMax Filippov2011-11-021-0/+6
* target-xtensa: mask out undefined bits of WINDOWSTART SRMax Filippov2011-11-021-1/+1
* target-xtensa: add fsf coreMax Filippov2011-10-162-0/+383
* target-xtensa: add dc232b coreMax Filippov2011-10-163-0/+712
* target-xtensa: extract core configuration from overlayMax Filippov2011-10-163-13/+554
* target-xtensa: implement external interrupt mappingMax Filippov2011-10-161-0/+3
* target-xtensa: remove hand-written xtensa cores implementationsMax Filippov2011-10-163-860/+2
* target-xtensa: increase xtensa options accuracyMax Filippov2011-10-162-8/+12
* target-xtensa: implement MAC16 optionMax Filippov2011-10-152-1/+137
* target-xtensa: fix guest hang on masked CCOMPARE interruptMax Filippov2011-10-152-15/+4
* softmmu_header: pass CPUState to tlb_fillBlue Swirl2011-10-011-2/+3
* target-xtensa: add dc232b core and boardMax Filippov2011-09-102-0/+429
* target-xtensa: implement boolean optionMax Filippov2011-09-102-24/+86
* target-xtensa: implement memory protection optionsMax Filippov2011-09-105-13/+782
* target-xtensa: add gdb supportMax Filippov2011-09-103-0/+400
* target-xtensa: implement relocatable vectorsMax Filippov2011-09-103-2/+19
* target-xtensa: implement CPENABLE and PRID SRsMax Filippov2011-09-102-0/+9
* target-xtensa: implement accurate window checkMax Filippov2011-09-101-0/+110
* target-xtensa: implement interrupt optionMax Filippov2011-09-105-12/+335
* target-xtensa: implement SIMCALLMax Filippov2011-09-102-1/+9
* target-xtensa: implement unaligned exception optionMax Filippov2011-09-103-4/+73
* target-xtensa: implement extended L32RMax Filippov2011-09-103-4/+40
* target-xtensa: implement loop optionMax Filippov2011-09-104-9/+93
* target-xtensa: implement windowed registersMax Filippov2011-09-105-9/+345
* target-xtensa: implement RST2 group (32 bit mul/div/rem)Max Filippov2011-09-101-1/+76
* target-xtensa: implement exceptionsMax Filippov2011-09-105-6/+236
* target-xtensa: add PS register and access controlMax Filippov2011-09-103-6/+77
* target-xtensa: implement CACHE groupMax Filippov2011-09-101-1/+94
* target-xtensa: implement SYNC groupMax Filippov2011-09-101-1/+30
* target-xtensa: mark reserved and TBD opcodesMax Filippov2011-09-101-1/+109
* target-xtensa: implement LSAI groupMax Filippov2011-09-102-0/+90
* target-xtensa: implement shifts (ST1 and RST1 groups)Max Filippov2011-09-104-0/+262
* target-xtensa: implement RST3 groupMax Filippov2011-09-101-0/+161
* target-xtensa: add special and user registersMax Filippov2011-09-102-2/+54
* target-xtensa: implement JX/RET0/CALLXMax Filippov2011-09-101-0/+43
* target-xtensa: implement conditional jumpsMax Filippov2011-09-101-0/+164
* target-xtensa: implement RT0 groupMax Filippov2011-09-101-0/+19
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