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* cpu: Add CPUArchState pointer to CPUStateAndreas Färber2013-02-161-0/+2
* target-xtensa: Move TCG initialization to XtensaCPU initfnAndreas Färber2013-02-163-13/+9
* target-xtensa: Introduce QOM realizefn for XtensaCPUAndreas Färber2013-02-163-1/+18
* target-xtensa: Mark as unmigratableAndreas Färber2013-02-013-39/+9
* target-xtensa: fix search_pc for the last TB opcodeMax Filippov2012-12-221-1/+5
* softmmu: move include files to include/sysemu/Paolo Bonzini2012-12-191-1/+1
* misc: move include files to include/qemu/Paolo Bonzini2012-12-197-7/+7
* qom: move include files to include/qom/Paolo Bonzini2012-12-191-1/+1
* exec: move include files to include/exec/Paolo Bonzini2012-12-198-19/+19
* build: kill libdis, move disassemblers to disas/Paolo Bonzini2012-12-191-1/+1
* exec: refactor cpu_restore_stateBlue Swirl2012-12-161-12/+2
* target-xtensa: fix ITLB/DTLB page protection flagsMax Filippov2012-12-151-1/+2
* target-xtensa: use movcond where possibleMax Filippov2012-12-081-50/+42
* target-xtensa: implement MISC SRMax Filippov2012-12-083-0/+6
* target-xtensa: better control rsr/wsr/xsr access to SRsMax Filippov2012-12-081-19/+30
* target-xtensa: restrict available SRs by enabled optionsMax Filippov2012-12-083-105/+130
* target-xtensa: implement CACHEATTR SRMax Filippov2012-12-085-1/+25
* target-xtensa: implement ATOMCTL SRMax Filippov2012-12-087-14/+131
* TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin2012-12-081-2/+2
* TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin2012-12-081-1/+1
* TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin2012-12-081-2/+2
* TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin2012-11-171-2/+2
* TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin2012-11-171-3/+3
* target-xtensa: avoid using cpu_single_envBlue Swirl2012-11-101-5/+5
* cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber2012-10-311-1/+3
* target-xtensa: rename helper flagsAurelien Jarno2012-10-281-8/+8
* Rename target_phys_addr_t to hwaddrAvi Kivity2012-10-232-4/+4
* target-xtensa: de-optimize EXTUIAurelien Jarno2012-10-061-20/+2
* Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson2012-09-271-1/+1
* target-xtensa: implement coprocessor context optionMax Filippov2012-09-222-0/+43
* target-xtensa: implement FP1 groupMax Filippov2012-09-223-1/+135
* target-xtensa: implement FP0 conversionsMax Filippov2012-09-223-0/+89
* target-xtensa: implement FP0 arithmeticMax Filippov2012-09-223-1/+104
* target-xtensa: implement LSCX and LSCI groupsMax Filippov2012-09-221-4/+54
* target-xtensa: add FP registersMax Filippov2012-09-224-7/+63
* target-xtensa: handle boolean option in overlaysMax Filippov2012-09-221-0/+1
* target-xtensa: don't emit extra tcg_gen_goto_tbMax Filippov2012-09-211-1/+3
* target-xtensa: fix extui shift amountMax Filippov2012-09-211-3/+21
* target-xtensa: fix missing errno codes for mingw32Max Filippov2012-09-081-0/+6
* target-xtensa: convert host errno values to guestMax Filippov2012-09-051-8/+98
* target-xtensa: return ENOSYS for unimplemented simcallsMax Filippov2012-09-011-0/+2
* Merge branch 'x86cpu_qom_tcg_v2' of git://github.com/imammedo/qemuBlue Swirl2012-08-091-7/+1
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| * target-xtensa: drop usage of prev_debug_excp_handlerIgor Mammedov2012-06-251-7/+1
* | target-xtensa: make default CPU depend on target endiannessMax Filippov2012-08-091-0/+6
* | target-xtensa: fix big-endian BBS/BBC implementationMax Filippov2012-07-281-2/+14
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* target-xtensa: switch to AREG0-free modeMax Filippov2012-06-104-154/+151
* target-xtensa: add attributes to helper functionsMax Filippov2012-06-101-8/+8
* target-xtensa: remove unnecessary include of dyngen-exec.hPeter Portante2012-06-101-1/+0
* target-xtensa: fix CCOUNT for conditional branchesMax Filippov2012-06-091-0/+2
* target-xtensa: control page table lookup explicitlyMax Filippov2012-06-091-5/+5
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