summaryrefslogtreecommitdiffstats
path: root/target-xtensa
Commit message (Expand)AuthorAgeFilesLines
* exec: Change cpu_memory_rw_debug() argument to CPUStateAndreas Färber2013-07-231-5/+5
* cpu: Turn cpu_get_phys_page_debug() into a CPUClass hookAndreas Färber2013-07-234-5/+10
* cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber2013-07-231-3/+4
* cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber2013-07-231-5/+0
* cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()Andreas Färber2013-07-231-0/+8
* target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPUAndreas Färber2013-07-091-4/+5
* target-xtensa: gen_intermediate_code_internal() should be inlinedAndreas Färber2013-07-091-2/+3
* cpu: Drop unnecessary dynamic casts in *_env_get_cpu()Andreas Färber2013-07-091-1/+1
* cpu: Change qemu_init_vcpu() argument to CPUStateAndreas Färber2013-06-281-3/+0
* cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber2013-06-284-3/+10
* cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber2013-03-124-2/+7
* cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber2013-03-121-1/+4
* gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell2013-03-031-2/+2
* cpu: Introduce ENV_OFFSET macrosAndreas Färber2013-03-031-0/+1
* target-xtensa: Use add2/sub2 for macRichard Henderson2013-02-231-16/+13
* target-xtensa: Use mul*2 for mul*hiRichard Henderson2013-02-231-14/+6
* cpu: Add CPUArchState pointer to CPUStateAndreas Färber2013-02-161-0/+2
* target-xtensa: Move TCG initialization to XtensaCPU initfnAndreas Färber2013-02-163-13/+9
* target-xtensa: Introduce QOM realizefn for XtensaCPUAndreas Färber2013-02-163-1/+18
* target-xtensa: Mark as unmigratableAndreas Färber2013-02-013-39/+9
* target-xtensa: fix search_pc for the last TB opcodeMax Filippov2012-12-221-1/+5
* softmmu: move include files to include/sysemu/Paolo Bonzini2012-12-191-1/+1
* misc: move include files to include/qemu/Paolo Bonzini2012-12-197-7/+7
* qom: move include files to include/qom/Paolo Bonzini2012-12-191-1/+1
* exec: move include files to include/exec/Paolo Bonzini2012-12-198-19/+19
* build: kill libdis, move disassemblers to disas/Paolo Bonzini2012-12-191-1/+1
* exec: refactor cpu_restore_stateBlue Swirl2012-12-161-12/+2
* target-xtensa: fix ITLB/DTLB page protection flagsMax Filippov2012-12-151-1/+2
* target-xtensa: use movcond where possibleMax Filippov2012-12-081-50/+42
* target-xtensa: implement MISC SRMax Filippov2012-12-083-0/+6
* target-xtensa: better control rsr/wsr/xsr access to SRsMax Filippov2012-12-081-19/+30
* target-xtensa: restrict available SRs by enabled optionsMax Filippov2012-12-083-105/+130
* target-xtensa: implement CACHEATTR SRMax Filippov2012-12-085-1/+25
* target-xtensa: implement ATOMCTL SRMax Filippov2012-12-087-14/+131
* TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin2012-12-081-2/+2
* TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin2012-12-081-1/+1
* TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin2012-12-081-2/+2
* TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin2012-11-171-2/+2
* TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin2012-11-171-3/+3
* target-xtensa: avoid using cpu_single_envBlue Swirl2012-11-101-5/+5
* cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber2012-10-311-1/+3
* target-xtensa: rename helper flagsAurelien Jarno2012-10-281-8/+8
* Rename target_phys_addr_t to hwaddrAvi Kivity2012-10-232-4/+4
* target-xtensa: de-optimize EXTUIAurelien Jarno2012-10-061-20/+2
* Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson2012-09-271-1/+1
* target-xtensa: implement coprocessor context optionMax Filippov2012-09-222-0/+43
* target-xtensa: implement FP1 groupMax Filippov2012-09-223-1/+135
* target-xtensa: implement FP0 conversionsMax Filippov2012-09-223-0/+89
* target-xtensa: implement FP0 arithmeticMax Filippov2012-09-223-1/+104
* target-xtensa: implement LSCX and LSCI groupsMax Filippov2012-09-221-4/+54
OpenPOWER on IntegriCloud