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* tcg: Change translator-side labels to a pointerRichard Henderson2015-03-131-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | This is improved type checking for the translators -- it's no longer possible to accidentally swap arguments to the branch functions. Note that the code generating backends still manipulate labels as int. With notable exceptions, the scope of the change is just a few lines for each target, so it's not worth building extra machinery to do this change in per-target increments. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-121-4/+3
| | | | | | | | The method by which we count the number of ops emitted is going to change. Abstract that away into some inlines. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson2015-02-121-1/+0
| | | | | Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* gen-icount: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-1/+1
| | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-xtensa: don't generate dead codeMax Filippov2014-12-171-279/+321
| | | | | | | | Don't generate TCG operations when privilege, register window or coprocessor checks fail. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-xtensa: record available window in TB flagsMax Filippov2014-12-171-43/+18
| | | | | | | | Record last valid 4-register window pane number in TB flags so that a window overflow exception throw point is known at the translation time. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-xtensa: fix translation for opcodes crossing page boundaryMax Filippov2014-12-171-4/+23
| | | | | | | | | | If TB ends with an opcode that crosses page boundary and the following page is not executable then EPC1 for the code fetch exception wrongly points at the beginning of the TB. Always treat instruction that crosses page boundary as a separate TB. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova2014-08-121-0/+3
| | | | | Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* softmmu: introduce cpu_ldst.hPaolo Bonzini2014-06-051-0/+1
| | | | | | | | | | This will collect all load and store helpers soon. For now it is just a replacement for softmmu_exec.h, which this patch stops including directly, but we also include it where this will be necessary in order to simplify the next patch. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-281-3/+2
| | | | | | | | | | Rather than include helper.h with N values of GEN_HELPER, include a secondary file that sets up the macros to include helper.h. This minimizes the files that must be rebuilt when changing the macros for file N. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-xtensa: fix cross-page jumps/calls at the end of TBMax Filippov2014-05-261-2/+2
| | | | | | | | | Use tb->pc instead of dc->pc to check for cross-page jumps. When TB translation stops at the page boundary dc->pc points to the next page allowing chaining to TBs in it, which is wrong. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-2/+3
| | | | | | | | Most targets were using offsetof(CPUFooState, breakpoints) to determine how much of CPUFooState to clear on reset. Use the next field after CPU_COMMON instead, if any, or sizeof(CPUFooState) otherwise. Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-xtensa: provide HW confg ID registersMax Filippov2014-02-241-2/+7
| | | | Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: add basic checks to icache opcodesMax Filippov2014-02-241-0/+27
| | | | | | | | | Check privilege level for privileged instructions (IHU, III, IIU and IPFL are privileged), memory accessibility for instructions that reference memory (IH* and IPFL) and windowed register validity for all instruction cache instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: add basic checks to dcache opcodesMax Filippov2014-02-241-0/+38
| | | | | | | | | Check privilege level for privileged instructions (DHI, DHU, DII, DIU, DIWB, DIWBI, DPFL are privileged), memory accessibility for instructions that reference memory (all DH* and DPFL) and windowed register validity for all data cache instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: add RRRI4 opcode format fieldsMax Filippov2014-02-241-0/+9
| | | | | | This encoding is used by cache instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: add in_asm loggingMax Filippov2013-10-151-0/+8
| | | | Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* tcg: Move helper registration into tcg_context_initRichard Henderson2013-10-101-2/+0
| | | | | | No longer needs to be done on a per-target basis. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson2013-09-021-1/+1
| | | | | | | And update all users. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-xtensa: check register window inlineMax Filippov2013-07-291-8/+25
| | | | | | | This lowers time spent in helper_window_check as reported by perf top from ~8% to ~0.15% accelerating register-intensive tests by ~20%. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: don't generate dead code to access invalid SRsMax Filippov2013-07-291-13/+18
| | | | | | | | | | | This fixes the following test failure caused by access to undefined SR: qemu-system-xtensa -M sim -cpu dc232b -nographic -semihosting -kernel ./test_sr.tst QEMU 1.4.50 monitor - type 'help' for more information (qemu) QEMU 1.4.50 monitor - type 'help' for more information (qemu) qemu-system-xtensa: tcg/tcg.c:1673: temp_save: Assertion `s->temps[temp].val_type == 2 || s->temps[temp].fixed_reg' failed. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: avoid double-stopping at breakpointsMax Filippov2013-07-291-2/+1
| | | | | | | | | | | | | env->exception_taken is set every time an exception is taken. It is used to allow single-stepping to stop at the first exception handler instruction. This however must exclude debug exceptions, as otherwise first step from the instruction where breakpoint was hit stops at that same instruction. Also don't check env->exception_taken directly from the gen_intermediate_code_internal, instead allocate and use TB flag XTENSA_TBFLAG_EXCEPTION. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber2013-07-231-3/+4
| | | | | | | Prepares for changing cpu_single_step() argument to CPUState. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPUAndreas Färber2013-07-091-4/+5
| | | | | | | | | Also use bool type while at it. Prepares for moving singlestep_enabled field to CPUState. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-xtensa: gen_intermediate_code_internal() should be inlinedAndreas Färber2013-07-091-2/+3
| | | | | | | Cc: qemu-stable@nongnu.org Reported-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber2013-06-281-2/+4
| | | | | | | | | Make cpustats monitor command available unconditionally. Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec() arguments to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
* gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell2013-03-031-2/+2
| | | | | | | | | | The gen_icount_start/end functions are now somewhat misnamed since they are useful for generic "start/end of TB" code, used for more than just icount. Rename them to gen_tb_start/end. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: Use add2/sub2 for macRichard Henderson2013-02-231-16/+13
| | | | | | Cc: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: Use mul*2 for mul*hiRichard Henderson2013-02-231-14/+6
| | | | | | Cc: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: fix search_pc for the last TB opcodeMax Filippov2012-12-221-1/+5
| | | | | | | | | Zero out tcg_ctx.gen_opc_instr_start for instructions representing the last guest opcode in the TB. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* softmmu: move include files to include/sysemu/Paolo Bonzini2012-12-191-1/+1
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* misc: move include files to include/qemu/Paolo Bonzini2012-12-191-1/+1
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* exec: move include files to include/exec/Paolo Bonzini2012-12-191-2/+2
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* build: kill libdis, move disassemblers to disas/Paolo Bonzini2012-12-191-1/+1
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-xtensa: use movcond where possibleMax Filippov2012-12-081-50/+42
| | | | | | | | Use movcond for all sorts of conditional moves, ABS, CLAMPS, MIN/MAX opcodes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement MISC SRMax Filippov2012-12-081-0/+4
| | | | | | | | | | | | The Miscellaneous Special Registers Option provides zero to four scratch registers within the processor readable and writable by RSR, WSR, and XSR. These registers are privileged. They may be useful for some application-specific exception and interrupt processing tasks in the kernel. The MISC registers are undefined after reset. See ISA, 4.7.3 for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: better control rsr/wsr/xsr access to SRsMax Filippov2012-12-081-19/+30
| | | | | | | | | There are read-only (DEBUGCAUSE, PRID) and write-only (INTCLEAR) SRs, and INTERRUPT/INTSET SR allows rsr/wsr, but not xsr. Raise illeagal opcode exception on illegal access to these SRs. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: restrict available SRs by enabled optionsMax Filippov2012-12-081-104/+126
| | | | | | | | | Beginning with the RA-2004.1 release, SR access instructions (rsr, wsr, xsr) are associated with their corresponding SR and raise illegal opcode exception in case the register is not configured for the core. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement CACHEATTR SRMax Filippov2012-12-081-0/+1
| | | | | | | | | | In XEA1, the Options for Memory Protection and Translation and the corresponding TLB management instructions are not available. Instead, functionality similar to the Region Protection Option is available through the cache attribute register. See ISA, A.2.14 for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement ATOMCTL SRMax Filippov2012-12-081-0/+13
| | | | | | | | ATOMCTL SR controls s32c1i opcode behavior depending on targeted memory type. See ISA, 4.3.12.4 for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin2012-12-081-2/+2
| | | | | Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin2012-12-081-1/+1
| | | | | Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin2012-12-081-2/+2
| | | | | Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin2012-11-171-2/+2
| | | | | | Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin2012-11-171-3/+3
| | | | | | Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: avoid using cpu_single_envBlue Swirl2012-11-101-5/+5
| | | | | | | | Pass around CPUArchState instead of using global cpu_single_env. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de>
* target-xtensa: de-optimize EXTUIAurelien Jarno2012-10-061-20/+2
| | | | | | | | | Now that "and" with 0xff, 0xffff and 0xffffffff and "shr" with 0 shift are optimized in tcg/tcg-op.h there is no need to do it in target-xtensa/translate.c. Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson2012-09-271-1/+1
| | | | | | | | | | | For all targets that currently call tcg_gen_debug_insn_start, add CPU_LOG_TB_OP_OPT to the condition that gates it. This is useful for comparing optimization dumps, when the pre-optimization dump is merely noise. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-xtensa: implement coprocessor context optionMax Filippov2012-09-221-0/+38
| | | | | | | | | | | | | In case Coprocessor Context option is enabled CPENABLE SR bits control whether access to coprocessors is allowed or would rise one of CoprocessorXDisabled exceptions. See ISA, 4.4.5 for more details. FP is coprocessor 0. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement FP1 groupMax Filippov2012-09-221-1/+80
| | | | | | | | These are comparison and conditional move opcodes. See ISA, 4.3.10 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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