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* target-xtensa: Don't overuse CPUStateAndreas Färber2012-03-141-11/+11
| | | | | | | | | Scripted conversion: sed -i "s/CPUState/CPUXtensaState/g" target-xtensa/*.[hc] sed -i "s/#define CPUXtensaState/#define CPUState/" target-xtensa/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
* target-xtensa: add DBREAK data breakpointsMax Filippov2012-02-201-0/+30
| | | | | | | | | | | | | Add DBREAKA/DBREAKC SRs and implement DBREAK breakpoints as debug watchpoints. This implementation is not fully compliant to ISA: when a breakpoint is set to an unmapped/inaccessible memory address it generates TLB/memory protection exception instead of debug exception. See ISA, 4.7.7.3, 4.7.7.6 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: add ICOUNT SR and debug exceptionMax Filippov2012-02-181-1/+48
| | | | | | | | | | | | | ICOUNT SR gets incremented on every instruction completion provided that CINTLEVEL at the beginning of the instruction execution is lower than ICOUNTLEVEL. When ICOUNT would increment to 0 a debug exception is raised if CINTLEVEL is lower than DEBUGLEVEL. See ISA, 4.7.7.5 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: implement instruction breakpointsMax Filippov2012-02-181-3/+65
| | | | | | | | | | Add IBREAKA/IBREAKENABLE SRs and implement debug exception, BREAK and BREAK.N instructions and IBREAK breakpoints. IBREAK breakpoint address is considered constant for TB lifetime. On IBREAKA/IBREAKENABLE change corresponding TBs are invalidated. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: add DEBUGCAUSE SR and configurationMax Filippov2012-02-181-0/+6
| | | | | | | DEBUGCAUSE SR holds information about the most recent debug exception. See ISA, 4.7.7 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: fetch 3rd opcode byte only when neededMax Filippov2012-02-181-1/+2
| | | | | | | According to ISA, 3.5.4, third opcode byte should not be fetched for 2-byte instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: raise an exception for invalid and reserved opcodesMax Filippov2011-11-021-1/+6
| | | | | | | | This includes opcodes from disabled features and those marked reserved in the ISA. Also end TB on opcodes that definitely generate an exception: illegal instructions, syscall and privileged instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: mask out undefined bits of WINDOWSTART SRMax Filippov2011-11-021-1/+1
| | | | | | | According to ISA, table 5-156, bits 32:NAREG/4 of the WINDOWSTART SR must be zero. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: increase xtensa options accuracyMax Filippov2011-10-161-7/+7
| | | | | | | | | - add separate options for each operation in the MISC_OP; - add an option for MULSH/MULUH; - put S32C1I under conditional store option. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement MAC16 optionMax Filippov2011-10-151-1/+134
| | | | | | | | | | See ISA, 4.3.7 for the details. - add ACC and MR special registers; - implement MAC16 and all inner MAC* opcode groups. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement boolean optionMax Filippov2011-09-101-24/+85
| | | | | | | See ISA, 4.3.9 Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement memory protection optionsMax Filippov2011-09-101-5/+86
| | | | | | | | | | | | - TLB opcode group; - region protection option (ISA, 4.6.3); - region translation option (ISA, 4.6.4); - MMU option (ISA, 4.6.5). Cache control attribute bits are not used by this implementation. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement relocatable vectorsMax Filippov2011-09-101-0/+1
| | | | | | | | | | See ISA, 4.4.3 for details. Vector addresses recorded in core configuration are absolute values that correspond to default VECBASE value. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement CPENABLE and PRID SRsMax Filippov2011-09-101-0/+7
| | | | | Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement accurate window checkMax Filippov2011-09-101-0/+110
| | | | | | | | | | | See ISA, 4.7.1.3 for details. Window check is inserted before commands that push "used register watermark" beyond its current level. Used register watermark is reset on instructions that change WINDOW_BASE/WINDOW_START SRs. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement interrupt optionMax Filippov2011-09-101-10/+143
| | | | | | | | See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interrupt option) and 4.4.8 (timer interrupt option) for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement SIMCALLMax Filippov2011-09-101-1/+8
| | | | | | | | | | | Tensilica iss provides support for applications running in freestanding environment through SIMCALL command. It is used by Tensilica libc to access argc/argv, for file I/O, etc. Note that simcalls that accept buffer addresses expect virtual addresses. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement unaligned exception optionMax Filippov2011-09-101-3/+44
| | | | | | | | | | See ISA, 4.4.4 for details. Correct (aligned as per ISA) address for unaligned access is generated in case this option is not enabled. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement extended L32RMax Filippov2011-09-101-4/+33
| | | | | | | | | See ISA, 4.3.3 for details. TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement loop optionMax Filippov2011-09-101-9/+68
| | | | | | | | | | | | | | | | | | See ISA, 4.3.2 for details. Operations that change LEND SR value invalidate TBs at the old and at the new LEND. LEND value at TB compilation time is considered constant and loop instruction is generated based on this value. Invalidation may be avoided for the TB at the old LEND address, since looping code verifies actual LEND value. Invalidation may be avoided for the TB at the new LEND address if there's a way to associate LEND address with TB at compilation time and later verify that it doesn't change. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement windowed registersMax Filippov2011-09-101-9/+136
| | | | | | | | | | | | | | See ISA, 4.7.1 for details. Physical registers and currently visible window are separate fields in CPUEnv. Only current window is accessible to TCG. On operations that change window base helpers copy current window to and from physical registers. Window overflow check described in 4.7.1.3 is in separate patch. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement RST2 group (32 bit mul/div/rem)Max Filippov2011-09-101-1/+76
| | | | | Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement exceptionsMax Filippov2011-09-101-5/+102
| | | | | | | | - mark privileged opcodes with ring check; - make debug exception on exception handler entry. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: add PS register and access controlMax Filippov2011-09-101-5/+24
| | | | | Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement CACHE groupMax Filippov2011-09-101-1/+94
| | | | | | | | | All operations in this group are no-ops, because cache ought to be transparent to applications. However cache may be abused, then we'll need to actually implement these opcodes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement SYNC groupMax Filippov2011-09-101-1/+30
| | | | | | | | All operations in this group are no-ops, because there are no delayed side effects. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: mark reserved and TBD opcodesMax Filippov2011-09-101-1/+109
| | | | | | | | | Reserved opcodes must generate illegal instruction exception. Usually they signal emulation quality problems. Not implemented opcodes are good to see. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement LSAI groupMax Filippov2011-09-101-0/+89
| | | | | | | | | - base + offset load/store operations for 1/2/4 byte values; - cache operations (not implemented); - multiprocessor synchronization operations. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement shifts (ST1 and RST1 groups)Max Filippov2011-09-101-0/+242
| | | | | | | | - ST1: SAR (shift amount special register) manipulation, NSA(U); - RST1: shifts, 16-bit multiplication. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement RST3 groupMax Filippov2011-09-101-0/+161
| | | | | | | | | | - access to Special Registers (wsr, rsr); - access to User Registers (wur, rur); - misc. operations option (value clamp, sign extension, min, max); - conditional moves. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: add special and user registersMax Filippov2011-09-101-2/+47
| | | | | | | | | | | | | Special Registers hold the majority of the state added to the processor by the options. See ISA, 5.3 for details. User Registers hold state added in support of designer's TIE and in some cases of options that Tensilica provides. See ISA, 5.4 for details. Only registers mapped in sregnames or uregnames are considered valid. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement JX/RET0/CALLXMax Filippov2011-09-101-0/+43
| | | | | | | Group SNM0 (indirect jumps and calls). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement conditional jumpsMax Filippov2011-09-101-0/+164
| | | | | | | | | | | - BZ (comparison to zero); - BI0 (comparison to signed immediate); - BI1 (comparison to unsigned immediate); - B (two registers comparison, bit sets comparison); - BEQZ.N/BNEZ.N (narrow comparison to zero). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement RT0 groupMax Filippov2011-09-101-0/+19
| | | | | | | NEG and ABS are the only members of RT0 group. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement narrow instructionsMax Filippov2011-09-101-0/+54
| | | | | | | Instructions with op0 >= 8 are 2 bytes long, others are 3 bytes long. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: implement disas_xtensa_insnMax Filippov2011-09-101-0/+452
| | | | | | | | | | Set up disas_xtensa_insn switch structure, mark required options on high level groups. Implement arithmetic/bit logic/jump/call0. Implement code generation loop with single step/breakpoint checking. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: add target stubsMax Filippov2011-09-101-0/+68
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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