hqemu - HQEMU

	Commit message (Expand)	Author	Age	Files	Lines
*	target-xtensa: avoid using cpu_single_env	Blue Swirl	2012-11-10	1	-5/+5
*	target-xtensa: de-optimize EXTUI	Aurelien Jarno	2012-10-06	1	-20/+2
*	Emit debug_insn for CPU_LOG_TB_OP_OPT as well.	Richard Henderson	2012-09-27	1	-1/+1
*	target-xtensa: implement coprocessor context option	Max Filippov	2012-09-22	1	-0/+38
*	target-xtensa: implement FP1 group	Max Filippov	2012-09-22	1	-1/+80
*	target-xtensa: implement FP0 conversions	Max Filippov	2012-09-22	1	-0/+48
*	target-xtensa: implement FP0 arithmetic	Max Filippov	2012-09-22	1	-1/+60
*	target-xtensa: implement LSCX and LSCI groups	Max Filippov	2012-09-22	1	-4/+54
*	target-xtensa: add FP registers	Max Filippov	2012-09-22	1	-7/+45
*	target-xtensa: don't emit extra tcg_gen_goto_tb	Max Filippov	2012-09-21	1	-1/+3
*	target-xtensa: fix extui shift amount	Max Filippov	2012-09-21	1	-3/+21
*	target-xtensa: fix big-endian BBS/BBC implementation	Max Filippov	2012-07-28	1	-2/+14
*	target-xtensa: switch to AREG0-free mode	Max Filippov	2012-06-10	1	-30/+34
*	target-xtensa: fix CCOUNT for conditional branches	Max Filippov	2012-06-09	1	-0/+2
*	target-xtensa: fix LOOPNEZ/LOOPGTZ translation	Max Filippov	2012-04-21	1	-1/+1
*	target-xtensa: fix tb invalidation for IBREAK and LOOP	Max Filippov	2012-04-14	1	-0/+2
*	target-xtensa: Move helpers.h to helper.h	Lluís Vilanova	2012-04-14	1	-3/+3
*	target-xtensa: Don't overuse CPUState	Andreas Färber	2012-03-14	1	-11/+11
*	target-xtensa: add DBREAK data breakpoints	Max Filippov	2012-02-20	1	-0/+30
*	target-xtensa: add ICOUNT SR and debug exception	Max Filippov	2012-02-18	1	-1/+48
*	target-xtensa: implement instruction breakpoints	Max Filippov	2012-02-18	1	-3/+65
*	target-xtensa: add DEBUGCAUSE SR and configuration	Max Filippov	2012-02-18	1	-0/+6
*	target-xtensa: fetch 3rd opcode byte only when needed	Max Filippov	2012-02-18	1	-1/+2
*	target-xtensa: raise an exception for invalid and reserved opcodes	Max Filippov	2011-11-02	1	-1/+6
*	target-xtensa: mask out undefined bits of WINDOWSTART SR	Max Filippov	2011-11-02	1	-1/+1
*	target-xtensa: increase xtensa options accuracy	Max Filippov	2011-10-16	1	-7/+7
*	target-xtensa: implement MAC16 option	Max Filippov	2011-10-15	1	-1/+134
*	target-xtensa: implement boolean option	Max Filippov	2011-09-10	1	-24/+85
*	target-xtensa: implement memory protection options	Max Filippov	2011-09-10	1	-5/+86
*	target-xtensa: implement relocatable vectors	Max Filippov	2011-09-10	1	-0/+1
*	target-xtensa: implement CPENABLE and PRID SRs	Max Filippov	2011-09-10	1	-0/+7
*	target-xtensa: implement accurate window check	Max Filippov	2011-09-10	1	-0/+110
*	target-xtensa: implement interrupt option	Max Filippov	2011-09-10	1	-10/+143
*	target-xtensa: implement SIMCALL	Max Filippov	2011-09-10	1	-1/+8
*	target-xtensa: implement unaligned exception option	Max Filippov	2011-09-10	1	-3/+44
*	target-xtensa: implement extended L32R	Max Filippov	2011-09-10	1	-4/+33
*	target-xtensa: implement loop option	Max Filippov	2011-09-10	1	-9/+68
*	target-xtensa: implement windowed registers	Max Filippov	2011-09-10	1	-9/+136
*	target-xtensa: implement RST2 group (32 bit mul/div/rem)	Max Filippov	2011-09-10	1	-1/+76
*	target-xtensa: implement exceptions	Max Filippov	2011-09-10	1	-5/+102
*	target-xtensa: add PS register and access control	Max Filippov	2011-09-10	1	-5/+24
*	target-xtensa: implement CACHE group	Max Filippov	2011-09-10	1	-1/+94
*	target-xtensa: implement SYNC group	Max Filippov	2011-09-10	1	-1/+30
*	target-xtensa: mark reserved and TBD opcodes	Max Filippov	2011-09-10	1	-1/+109
*	target-xtensa: implement LSAI group	Max Filippov	2011-09-10	1	-0/+89
*	target-xtensa: implement shifts (ST1 and RST1 groups)	Max Filippov	2011-09-10	1	-0/+242
*	target-xtensa: implement RST3 group	Max Filippov	2011-09-10	1	-0/+161
*	target-xtensa: add special and user registers	Max Filippov	2011-09-10	1	-2/+47
*	target-xtensa: implement JX/RET0/CALLX	Max Filippov	2011-09-10	1	-0/+43
*	target-xtensa: implement conditional jumps	Max Filippov	2011-09-10	1	-0/+164