hqemu - HQEMU

	Commit message (Expand)	Author	Age	Files	Lines
*	target-xtensa: fix build for cores w/o windowed registers	Max Filippov	2014-11-03	1	-12/+19
*	target-xtensa: add definition for XTHAL_INTTYPE_PROFILING	Max Filippov	2014-11-03	1	-0/+1
*	target-xtensa: provide HW confg ID registers	Max Filippov	2014-02-24	1	-1/+8
*	target-xtensa: refactor standard core configuration	Max Filippov	2014-02-24	1	-0/+10
*	target-xtensa: implement MISC SR	Max Filippov	2012-12-08	1	-0/+1
*	target-xtensa: restrict available SRs by enabled options	Max Filippov	2012-12-08	1	-1/+3
*	target-xtensa: implement CACHEATTR SR	Max Filippov	2012-12-08	1	-0/+1
*	target-xtensa: implement ATOMCTL SR	Max Filippov	2012-12-08	1	-0/+6
*	target-xtensa: handle boolean option in overlays	Max Filippov	2012-09-22	1	-0/+1
*	target-xtensa: add DEBUG_SECTION to overlay tool	Max Filippov	2012-02-20	1	-0/+5
*	target-xtensa: define TLB_TEMPLATE for MMU-less cores	Max Filippov	2012-02-18	1	-2/+16
*	target-xtensa: fix MMUv3 initialization	Max Filippov	2011-11-26	1	-1/+1
*	target-xtensa: handle cache options in the overlay tool	Max Filippov	2011-11-02	1	-0/+6
*	target-xtensa: extract core configuration from overlay	Max Filippov	2011-10-16	1	-0/+534