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* target-tricore: Fix check which was always falseStefan Weil2015-04-041-1/+1
* target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..Bastian Koppelmann2015-03-301-4/+4
* target-tricore: properly fix dvinit_b/h_13Bastian Koppelmann2015-03-241-30/+10
* target-tricore: fix RRPW_DEXTR using wrong regBastian Koppelmann2015-03-241-2/+2
* target-tricore: fix DVINIT_HU/BU calculating overflow before resultBastian Koppelmann2015-03-241-12/+18
* target-tricore: Fix two helper functions (clang warnings)Stefan Weil2015-03-241-6/+6
* Fix typos in commentsViswesh2015-03-191-11/+11
* target-tricore: Add instructions of SYS opcode formatBastian Koppelmann2015-03-164-0/+175
* target-tricore: Add instructions of RRRW opcode formatBastian Koppelmann2015-03-161-0/+63
* target-tricore: Add instructions of RRRR opcode formatBastian Koppelmann2015-03-161-0/+56
* target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi...Bastian Koppelmann2015-03-164-2/+415
* target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi...Bastian Koppelmann2015-03-164-2/+600
* target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi...Bastian Koppelmann2015-03-164-24/+493
* tcg: Change translator-side labels to a pointerRichard Henderson2015-03-131-4/+2
* cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost2015-03-101-9/+1
* target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as fi...Bastian Koppelmann2015-03-033-0/+418
* target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as fi...Bastian Koppelmann2015-03-034-4/+588
* target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as fi...Bastian Koppelmann2015-03-033-0/+534
* target-tricore: Add instructions of RRR2 opcode formatBastian Koppelmann2015-03-032-15/+136
* target-tricore: fix msub32_suov return wrong resultsBastian Koppelmann2015-03-031-6/+21
* target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helperBastian Koppelmann2015-03-031-2/+2
* tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-121-3/+1
* tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson2015-02-121-1/+0
* target-tricore: Add instructions of RRR opcode formatBastian Koppelmann2015-01-274-1/+319
* target-tricore: Add instructions of RRPW opcode formatBastian Koppelmann2015-01-271-0/+70
* target-tricore: Add instructions of RR2 opcode formatBastian Koppelmann2015-01-271-0/+37
* target-tricore: Add instructions of RR1 opcode format, that have 0x93 as firs...Bastian Koppelmann2015-01-271-0/+182
* target-tricore: split up suov32 into suov32_pos and suov32_negBastian Koppelmann2015-01-261-15/+26
* target-tricore: Fix bugs found by coverityBastian Koppelmann2015-01-262-1/+3
* target-tricore: calculate av bits before saturationBastian Koppelmann2015-01-261-12/+16
* target-tricore: Several translator and cpu model fixesBastian Koppelmann2015-01-263-4/+5
* target-tricore: Add missing ULL suffix on 64 bit constantPeter Maydell2015-01-261-1/+1
* target-tricore: Fix new typosStefan Weil2015-01-153-4/+4
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2015-01-091-1/+1
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| * gen-icount: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-1/+1
* | target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as firs...Bastian Koppelmann2014-12-213-0/+273
* | target-tricore: Fix MFCR/MTCR insn and B format offset.Bastian Koppelmann2014-12-212-2/+6
* | target-tricore: Add missing 1.6 insn of BOL opcode formatBastian Koppelmann2014-12-212-1/+54
* | target-tricore: Add instructions of RR opcode format, that have 0x4b as the f...Bastian Koppelmann2014-12-214-1/+390
* | target-tricore: Add instructions of RR opcode format, that have 0x1 as the fi...Bastian Koppelmann2014-12-211-0/+97
* | target-tricore: Add instructions of RR opcode format, that have 0xf as the fi...Bastian Koppelmann2014-12-213-0/+250
* | target-tricore: Add instructions of RR opcode format, that have 0xb as the fi...Bastian Koppelmann2014-12-214-2/+942
* | target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32Bastian Koppelmann2014-12-211-76/+58
* | target-tricore: Fix mask handling JNZ.T being 7 bit longBastian Koppelmann2014-12-211-2/+2
* | target-tricore: pretty-print register dump and show more status registersAlex Zuepke2014-12-211-6/+15
* | target-tricore: add missing 64-bit MOV in RLC formatAlex Zuepke2014-12-212-0/+13
* | target-tricore: typo in BOL formatAlex Zuepke2014-12-212-3/+3
* | target-tricore: fix offset masking in BOL formatAlex Zuepke2014-12-211-1/+1
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* target-tricore: Add instructions of RCR opcode formatBastian Koppelmann2014-12-104-1/+657
* target-tricore: Add instructions of RLC opcode formatBastian Koppelmann2014-12-105-0/+252
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