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* tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-121-3/+1
| | | | | | | | The method by which we count the number of ops emitted is going to change. Abstract that away into some inlines. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson2015-02-121-1/+0
| | | | | Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RRR opcode formatBastian Koppelmann2015-01-274-1/+319
| | | | | | | | | | | | | | | | | Add microcode generator function gen_cond_sub. Add helper functions: * ixmax/ixmin: search for the max/min value and its related index in a vector of 16-bit values. * pack: dack two data registers into an IEEE-754 single precision floating point format number. * dvadj: divide-adjust the result after dvstep instructions. * dvstep: divide a reg by a divisor, producing 8-bits of quotient at a time. OPCM_32_RRR_FLOAT -> OPCM_32_RRR_DIVIDE Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RRPW opcode formatBastian Koppelmann2015-01-271-0/+70
| | | | | Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RR2 opcode formatBastian Koppelmann2015-01-271-0/+37
| | | | | Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RR1 opcode format, that have 0x93 as ↵Bastian Koppelmann2015-01-271-0/+182
| | | | | | | first opcode Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: split up suov32 into suov32_pos and suov32_negBastian Koppelmann2015-01-261-15/+26
| | | | | | | | | | | | | | | | | suov checks unsigned for an overflow and an underflow, after some arithmetic operations and saturates the result to either max_uint32 or 0. So far we handled this by expanding to the next bigger data type and compare whether the result is > max_uint32 or < 0. However this approach can fail for an 32 bit multiplication, if both operands of the multiplication are 0x80000000. This sets the sign bit of the 64 bit integer and would result in a false saturation to 0. Since unsigned operations, e.g add, sub, mul always result in either a positive or negative overflow, we split the functions for suov32 up into two functions (suov32_pos, suov32_neg) for each case. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: Fix bugs found by coverityBastian Koppelmann2015-01-262-1/+3
| | | | | | | | | | | | This fixes one bug and one false positive found by coverity. The bug is, that gen_mtcr was missing a mask to check the flag, which resulted in dead code. The false positive is a intentional missing break for a jump and link address insn followed by a jump and link insn. This adds a fall through comment to avoid the false positive in the future. Reported-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: calculate av bits before saturationBastian Koppelmann2015-01-261-12/+16
| | | | | | | | 64 bit mac instructions calculated the av bits after the saturation, which resulted in a wrong PSW. This moves the av bit calculation before the saturation. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: Several translator and cpu model fixesBastian Koppelmann2015-01-263-4/+5
| | | | | | | | Fix tc1796 cpu model using wrong ISA version. Fix cond_add sometimes writing back wrong result. Fix RCR_SEL and RCR_SELN using wrong registers for result and cond. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: Add missing ULL suffix on 64 bit constantPeter Maydell2015-01-261-1/+1
| | | | | | | | Add a missing ULL suffix to a 64 bit constant: this suppresses a compiler warning from mingw32 gcc. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: Fix new typosStefan Weil2015-01-153-4/+4
| | | | | | | | | adress -> address managment -> management Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2015-01-091-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | More migration fixes and more record/replay preparations. Also moves the sdhci-pci device id to make space for the rocker device. # gpg: Signature made Sat 03 Jan 2015 08:22:36 GMT using RSA key ID 78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: pci: move REDHAT_SDHCI device ID to make room for Rocker block/iscsi: fix uninitialized variable pckbd: set bits 2-3-6-7 of the output port by default serial: refine serial_thr_ipending_needed gen-icount: check cflags instead of use_icount global translate: check cflags instead of use_icount global cpu-exec: add a new CF_USE_ICOUNT cflag target-ppc: pass DisasContext to SPR generator functions atomic: fix position of volatile qualifier Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * gen-icount: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-1/+1
| | | | | | | | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as ↵Bastian Koppelmann2014-12-213-0/+273
| | | | | | | | | | | | | | | | | | | | | | | | first opcode Add instructions of RR1 opcode format, that have 0xb3 as first opcode. Add helper functions mulh, mulmh and mulrh, that compute multiplication, with multiprecision (mulmh) or rounding (mulrh) of 4 halfwords, being either low or high parts of two 32 bit regs. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* | target-tricore: Fix MFCR/MTCR insn and B format offset.Bastian Koppelmann2014-12-212-2/+6
| | | | | | | | | | | | | | | | | | Fix gen_mtcr using wrong register. Fix gen_mtcr/mfcr using sign extended offsets. Fix B format insn using not sign extendend offsets. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* | target-tricore: Add missing 1.6 insn of BOL opcode formatBastian Koppelmann2014-12-212-1/+54
| | | | | | | | | | | | | | Some of the 1.6 ISA instructions were still missing. So let's add them. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* | target-tricore: Add instructions of RR opcode format, that have 0x4b as the ↵Bastian Koppelmann2014-12-214-1/+390
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | first opcode Add instructions of RR opcode format, that have 0x4b as the first opcode. Add helper functions: * parity: Calculates the parity bits for every byte of a 32 int. * bmerge/bsplit: Merges two regs into one bitwise/Splits one reg into two bitwise. * unpack: unpack a IEEE 754 single precision floating point number as exponent and mantissa. * dvinit_b_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation, where the quotient result is guaranteed to fit into 8 bit. * dvinit_h_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation, where the quotient result is guaranteed to fit into 16 bit. OPCM_32_RR_FLOAT -> OPCM_32_RR_DIVIDE. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* | target-tricore: Add instructions of RR opcode format, that have 0x1 as the ↵Bastian Koppelmann2014-12-211-0/+97
| | | | | | | | | | | | | | | | | | first opcode Add instructions of RR opcode format, that have 0x1 as the first opcode. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* | target-tricore: Add instructions of RR opcode format, that have 0xf as the ↵Bastian Koppelmann2014-12-213-0/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | | | first opcode Add instructions of RR opcode format, that have 0xf as the first opcode. Add helper functions: * clo/z/s: Counts leading ones/zeros/signs. * clo/z/s_h: Count leading ones/zeros/signs in two haflwords. * sh/_h: Shifts one/two word/hwords. * sha/_h: Shifts one/two word/hwords arithmeticly. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* | target-tricore: Add instructions of RR opcode format, that have 0xb as the ↵Bastian Koppelmann2014-12-214-2/+942
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | first opcode Add instructions of RR opcode format, that have 0xb as the first opcode. Add helper functions, for hword and byte arithmetics: * add_h_ssov/suov: Add two halfword and saturate on overflow. * sub_h_ssov/suov: Sub two halfword and saturate on overflow. * absdif_h_ssov: Compute absolute difference for halfwords and saturate on overflow. * abs_h_ssov/suov: Compute absolute value for two halfwords and saturate on overflow. * abs_b/h: Compute absolute value for four/two bytes/halfwords * absdif_b/h: Compute absolute difference for four/two bytes/halfwords * add_b/h: Add four/two bytes/halfwords. * sub_b/h: Sub four/two bytes/halfwords. * eq_b/h: Compare four/two bytes/halfwords with four/two bytes/halfwords on equality and set all bits of to either one ore zero. * eqany_b/h: Compare four/two bytes/halfwords with four/two bytes/halfwords on equality. * lt_b/bu/h/hu: Compare four/two bytes/halfwords with four/two bytes/halfwords on less than signed and unsigned. * max_b/bu/h/hu: Calculate max for four/two bytes/halfwords signed and unsigned. * min_b/bu/h/hu: Calculate min for four/two bytes/halfwords signed and unsigned. Add helper function abs_ssov, that computes the absolute value for a 32 bit integer and saturates on overflow. Add microcode generator functions: * gen_sub_CC: Caluclates sub and sets the carry bit. * gen_subc_CC: Caluclates sub and carry and sets the carry bit * gen_abs: Compute absolute value for a 32 bit integer. * gen_cond_w: Compares two 32 bit values on cond and sets result either zero or all bits one. OPC2_32_RR_MIN switched with OPC2_32_RR_MIN_U. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* | target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32Bastian Koppelmann2014-12-211-76/+58
| | | | | | | | | | | | | | | | | | | | Those makros are exclusively used for 32 bit arithmetics and won't work for 16 bit with two halfwords. So lets get rid of the len parameter and make them always use 32 bit. Now no token pasting is needed anymore and they can be regular functions. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* | target-tricore: Fix mask handling JNZ.T being 7 bit longBastian Koppelmann2014-12-211-2/+2
| | | | | | | | | | | | | | The mask is actually 7 bit long, instead of 6, so the expression checking for JNZ.T is always false. Let's make the mask 1 bit wider. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* | target-tricore: pretty-print register dump and show more status registersAlex Zuepke2014-12-211-6/+15
| | | | | | | | | | | | | | | | Now using psw_read() to retrieve the status bits correctly. Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* | target-tricore: add missing 64-bit MOV in RLC formatAlex Zuepke2014-12-212-0/+13
| | | | | | | | | | | | Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* | target-tricore: typo in BOL formatAlex Zuepke2014-12-212-3/+3
| | | | | | | | | | | | Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* | target-tricore: fix offset masking in BOL formatAlex Zuepke2014-12-211-1/+1
|/ | | | | | Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: Add instructions of RCR opcode formatBastian Koppelmann2014-12-104-1/+657
| | | | | | | | | | | Add instructions of RCR opcode format. Add helper for madd32/64_ssov and madd32/64_suov. Add helper for msub32/64_ssov and msub32/64_suov. Add microcode generator function madd/msub for 32bit and 64bit, which calculate a mul and a add/sub. OPC2_32_RCR_MSUB_U_32 -> OPC2_32_RCR_MSUB_U_32. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RLC opcode formatBastian Koppelmann2014-12-105-0/+252
| | | | | | | | | Add instructions of RLC opcode format. Add helper psw_write/read. Add microcode generator gen_mtcr/mfcr, which loads/stores a value to a core special function register, which are defined in csfr.def Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RCPW, RCRR and RCRW opcode formatBastian Koppelmann2014-12-101-3/+129
| | | | | | | | Add instructions of RCPW, RCRR and RCRW opcode format. Add microcode generator function gen_insert. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Make TRICORE_FEATURES implying others.Bastian Koppelmann2014-12-102-3/+12
| | | | | | | | | Since all the TriCore instructionsets are subsets of each other (1.3 C 1.3.1 C 1.6), make the features implying each other, e.g 1.6 also has 1.3.1 and 1.3. This way we only need to check our features for the instructionset, where a instruction was first introduced. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RC opcode formatBastian Koppelmann2014-12-104-0/+799
| | | | | | | | | | | | | | | | | | | | Add instructions of RC opcode format. Add helper for mul, sha, absdif with signed saturation on overflow. Add helper for add, sub, mul with unsigned saturation on overflow. Add microcode generator functions: * gen_add_CC, which calculates the carry bit. * gen_addc_CC, which adds the carry bit to the add and calculates the carry bit. * gen_absdif, which calculates the absolute difference. * gen_mul_i64s/u, which mul two 32 bits val into one 64bit reg. * gen_sh_hi, which shifts two 16bit words in one reg. * gen_sha_hi, which does a arithmetic shift on two 16bit words. * gen_sh_cond, which shifts left a reg by one and writes the result of cond into the lsb. * gen_accumulating_cond, which ands/ors/xors the result of cond of the lsbs with the lsb of the result. * gen_eqany_bi/hi, which checks ever byte/hword on equality. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of BRR opcode formatBastian Koppelmann2014-12-102-2/+89
| | | | | | | | Add instructions of BRR opcode format. Add MASK_OP_BRR_DISP15_SEXT. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of BRN opcode formatBastian Koppelmann2014-12-102-0/+27
| | | | | | | | Add instructions of BRN opcode format. Add MASK_OP_BRN_DISP15_SEXT. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of BRC opcode formatBastian Koppelmann2014-12-102-3/+56
| | | | | | | | Add instructions of BRC opcode format. Fixed OP2_BRC_JGE -> OP2_32_BRC_JGE Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of BOL opcode formatBastian Koppelmann2014-12-102-1/+51
| | | | | | | Add instructions of BOL opcode format. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of BO opcode formatBastian Koppelmann2014-10-204-0/+704
| | | | | | | | | | | Add instructions of BO opcode format. Add microcode generator functions gen_swap, gen_ldmst. Add microcode generator functions gen_st/ld_preincr, which write back the address after the memory access. Add helper for circular and bit reverse addr mode calculation. Add sign extended bitmask for BO_OFF10 field. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of BIT opcode formatBastian Koppelmann2014-10-201-0/+312
| | | | | | | | Add instructions of BIT opcode format. Add microcode generator functions gen_bit_1/2op to do 1/2 bit operations on the last bit. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of B opcode formatBastian Koppelmann2014-10-201-0/+27
| | | | | | | Add instructions of B opcode format. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of ABS, ABSB opcode formatBastian Koppelmann2014-10-203-0/+352
| | | | | | | | | | Add instructions of ABS, ABSB opcode format. Add microcode generator functions for ld/st of two 32bit reg as one 64bit value. Add microcode generator functions for ldmst and swap. Add helper ldlcx, lducx, stlcx and stucx. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Cleanup and BugfixesBastian Koppelmann2014-10-202-27/+22
| | | | | | | | | | | Move FCX loading of save_context_ to caller functions, for STLCX, STUCX insn to use those functions. Move FCX storing of restore_context_ to caller functions, for LDLCX, LDUCX insn to use those functions. Remove do_raise_exception function, which caused clang to emit a warning. Fix: save_context_lower now saves a[11] instead of PSW. Fix: MASK_OP_ABSB_BPOS starting at wrong offset. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Remove the dummy interrupt boilerplateRichard Henderson2014-09-254-8/+0
| | | | | | | | | | It can go back in when it actually does something. Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-id: 1410626734-3804-18-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-tricore: Add instructions of SR opcode formatBastian Koppelmann2014-09-013-0/+164
| | | | | | | | | | Add instructions of SR opcode format. Add micro-op generator functions for saturate. Add helper return from exception (rfe). Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-id: 1409572800-4116-16-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-tricore: Add instructions of SLR, SSRO and SRO opcode formatBastian Koppelmann2014-09-011-0/+121
| | | | | | | | | | Add instructions of SLR, SSRO and SRO opcode format. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1409572800-4116-15-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-tricore: Add instructions of SC opcode formatBastian Koppelmann2014-09-013-0/+108
| | | | | | | | | Add instructions of SC opcode format. Add helper for begin interrupt service routine. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-id: 1409572800-4116-14-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-tricore: Add instructions of SBR opcode formatBastian Koppelmann2014-09-011-1/+65
| | | | | | | | | | | Add instructions of SBR opcode format. Add gen_loop micro-op generator function. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1409572800-4116-13-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-tricore: Add instructions of SBC and SBRN opcode formatBastian Koppelmann2014-09-011-0/+36
| | | | | | | | | | Add instructions of SBC and SBRN opcode format. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1409572800-4116-12-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-tricore: Add instructions of SB opcode formatBastian Koppelmann2014-09-013-0/+276
| | | | | | | | | | | Add instructions of SB opcode format. Add helper call/ret. Add micro-op generator functions for branches. Add makro to generate helper functions. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-id: 1409572800-4116-11-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-tricore: Add instructions of SRRS and SLRO opcode formatBastian Koppelmann2014-09-011-0/+59
| | | | | | | | | | | Add instructions of SSRS and SLRO opcode format. Add micro-op generator functions for offset loads. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1409572800-4116-10-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-tricore: Add instructions of SSR opcode formatBastian Koppelmann2014-09-011-0/+50
| | | | | | | | | | Add instructions of SSR opcode format. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1409572800-4116-9-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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