hqemu - HQEMU

	Commit message (Expand)	Author	Age	Files	Lines
*	tcg: Introduce tcg_op_buf_count and tcg_op_buf_full	Richard Henderson	2015-02-12	1	-3/+1
*	tcg: Move emit of INDEX_op_end into gen_tb_end	Richard Henderson	2015-02-12	1	-1/+0
*	target-tricore: Add instructions of RRR opcode format	Bastian Koppelmann	2015-01-27	4	-1/+319
*	target-tricore: Add instructions of RRPW opcode format	Bastian Koppelmann	2015-01-27	1	-0/+70
*	target-tricore: Add instructions of RR2 opcode format	Bastian Koppelmann	2015-01-27	1	-0/+37
*	target-tricore: Add instructions of RR1 opcode format, that have 0x93 as firs...	Bastian Koppelmann	2015-01-27	1	-0/+182
*	target-tricore: split up suov32 into suov32_pos and suov32_neg	Bastian Koppelmann	2015-01-26	1	-15/+26
*	target-tricore: Fix bugs found by coverity	Bastian Koppelmann	2015-01-26	2	-1/+3
*	target-tricore: calculate av bits before saturation	Bastian Koppelmann	2015-01-26	1	-12/+16
*	target-tricore: Several translator and cpu model fixes	Bastian Koppelmann	2015-01-26	3	-4/+5
*	target-tricore: Add missing ULL suffix on 64 bit constant	Peter Maydell	2015-01-26	1	-1/+1
*	target-tricore: Fix new typos	Stefan Weil	2015-01-15	3	-4/+4
*	Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging	Peter Maydell	2015-01-09	1	-1/+1
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\| *	gen-icount: check cflags instead of use_icount global	Paolo Bonzini	2015-01-03	1	-1/+1
* \|	target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as firs...	Bastian Koppelmann	2014-12-21	3	-0/+273
* \|	target-tricore: Fix MFCR/MTCR insn and B format offset.	Bastian Koppelmann	2014-12-21	2	-2/+6
* \|	target-tricore: Add missing 1.6 insn of BOL opcode format	Bastian Koppelmann	2014-12-21	2	-1/+54
* \|	target-tricore: Add instructions of RR opcode format, that have 0x4b as the f...	Bastian Koppelmann	2014-12-21	4	-1/+390
* \|	target-tricore: Add instructions of RR opcode format, that have 0x1 as the fi...	Bastian Koppelmann	2014-12-21	1	-0/+97
* \|	target-tricore: Add instructions of RR opcode format, that have 0xf as the fi...	Bastian Koppelmann	2014-12-21	3	-0/+250
* \|	target-tricore: Add instructions of RR opcode format, that have 0xb as the fi...	Bastian Koppelmann	2014-12-21	4	-2/+942
* \|	target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32	Bastian Koppelmann	2014-12-21	1	-76/+58
* \|	target-tricore: Fix mask handling JNZ.T being 7 bit long	Bastian Koppelmann	2014-12-21	1	-2/+2
* \|	target-tricore: pretty-print register dump and show more status registers	Alex Zuepke	2014-12-21	1	-6/+15
* \|	target-tricore: add missing 64-bit MOV in RLC format	Alex Zuepke	2014-12-21	2	-0/+13
* \|	target-tricore: typo in BOL format	Alex Zuepke	2014-12-21	2	-3/+3
* \|	target-tricore: fix offset masking in BOL format	Alex Zuepke	2014-12-21	1	-1/+1
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*	target-tricore: Add instructions of RCR opcode format	Bastian Koppelmann	2014-12-10	4	-1/+657
*	target-tricore: Add instructions of RLC opcode format	Bastian Koppelmann	2014-12-10	5	-0/+252
*	target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format	Bastian Koppelmann	2014-12-10	1	-3/+129
*	target-tricore: Make TRICORE_FEATURES implying others.	Bastian Koppelmann	2014-12-10	2	-3/+12
*	target-tricore: Add instructions of RC opcode format	Bastian Koppelmann	2014-12-10	4	-0/+799
*	target-tricore: Add instructions of BRR opcode format	Bastian Koppelmann	2014-12-10	2	-2/+89
*	target-tricore: Add instructions of BRN opcode format	Bastian Koppelmann	2014-12-10	2	-0/+27
*	target-tricore: Add instructions of BRC opcode format	Bastian Koppelmann	2014-12-10	2	-3/+56
*	target-tricore: Add instructions of BOL opcode format	Bastian Koppelmann	2014-12-10	2	-1/+51
*	target-tricore: Add instructions of BO opcode format	Bastian Koppelmann	2014-10-20	4	-0/+704
*	target-tricore: Add instructions of BIT opcode format	Bastian Koppelmann	2014-10-20	1	-0/+312
*	target-tricore: Add instructions of B opcode format	Bastian Koppelmann	2014-10-20	1	-0/+27
*	target-tricore: Add instructions of ABS, ABSB opcode format	Bastian Koppelmann	2014-10-20	3	-0/+352
*	target-tricore: Cleanup and Bugfixes	Bastian Koppelmann	2014-10-20	2	-27/+22
*	target-tricore: Remove the dummy interrupt boilerplate	Richard Henderson	2014-09-25	4	-8/+0
*	target-tricore: Add instructions of SR opcode format	Bastian Koppelmann	2014-09-01	3	-0/+164
*	target-tricore: Add instructions of SLR, SSRO and SRO opcode format	Bastian Koppelmann	2014-09-01	1	-0/+121
*	target-tricore: Add instructions of SC opcode format	Bastian Koppelmann	2014-09-01	3	-0/+108
*	target-tricore: Add instructions of SBR opcode format	Bastian Koppelmann	2014-09-01	1	-1/+65
*	target-tricore: Add instructions of SBC and SBRN opcode format	Bastian Koppelmann	2014-09-01	1	-0/+36
*	target-tricore: Add instructions of SB opcode format	Bastian Koppelmann	2014-09-01	3	-0/+276
*	target-tricore: Add instructions of SRRS and SLRO opcode format	Bastian Koppelmann	2014-09-01	1	-0/+59
*	target-tricore: Add instructions of SSR opcode format	Bastian Koppelmann	2014-09-01	1	-0/+50