| Commit message (Expand) | Author | Age | Files | Lines |
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| * | tcg: Delete unused cpu_pc_from_tb() | Peter Crosthwaite | 2015-04-30 | 1 | -5/+0 |
| * | target-tricore: Fix check which was always false | Stefan Weil | 2015-04-04 | 1 | -1/+1 |
| * | target-tricore: fix CACHEA/I_POSTINC/PREINC using data register.. | Bastian Koppelmann | 2015-03-30 | 1 | -4/+4 |
| * | target-tricore: properly fix dvinit_b/h_13 | Bastian Koppelmann | 2015-03-24 | 1 | -30/+10 |
| * | target-tricore: fix RRPW_DEXTR using wrong reg | Bastian Koppelmann | 2015-03-24 | 1 | -2/+2 |
| * | target-tricore: fix DVINIT_HU/BU calculating overflow before result | Bastian Koppelmann | 2015-03-24 | 1 | -12/+18 |
| * | target-tricore: Fix two helper functions (clang warnings) | Stefan Weil | 2015-03-24 | 1 | -6/+6 |
| * | Fix typos in comments | Viswesh | 2015-03-19 | 1 | -11/+11 |
| * | target-tricore: Add instructions of SYS opcode format | Bastian Koppelmann | 2015-03-16 | 4 | -0/+175 |
| * | target-tricore: Add instructions of RRRW opcode format | Bastian Koppelmann | 2015-03-16 | 1 | -0/+63 |
| * | target-tricore: Add instructions of RRRR opcode format | Bastian Koppelmann | 2015-03-16 | 1 | -0/+56 |
| * | target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi... | Bastian Koppelmann | 2015-03-16 | 4 | -2/+415 |
| * | target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi... | Bastian Koppelmann | 2015-03-16 | 4 | -2/+600 |
| * | target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi... | Bastian Koppelmann | 2015-03-16 | 4 | -24/+493 |
| * | tcg: Change translator-side labels to a pointer | Richard Henderson | 2015-03-13 | 1 | -4/+2 |
| * | cpu: Make cpu_init() return QOM CPUState object | Eduardo Habkost | 2015-03-10 | 1 | -9/+1 |
| * | target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as fi... | Bastian Koppelmann | 2015-03-03 | 3 | -0/+418 |
| * | target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as fi... | Bastian Koppelmann | 2015-03-03 | 4 | -4/+588 |
| * | target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as fi... | Bastian Koppelmann | 2015-03-03 | 3 | -0/+534 |
| * | target-tricore: Add instructions of RRR2 opcode format | Bastian Koppelmann | 2015-03-03 | 2 | -15/+136 |
| * | target-tricore: fix msub32_suov return wrong results | Bastian Koppelmann | 2015-03-03 | 1 | -6/+21 |
| * | target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper | Bastian Koppelmann | 2015-03-03 | 1 | -2/+2 |
| * | tcg: Introduce tcg_op_buf_count and tcg_op_buf_full | Richard Henderson | 2015-02-12 | 1 | -3/+1 |
| * | tcg: Move emit of INDEX_op_end into gen_tb_end | Richard Henderson | 2015-02-12 | 1 | -1/+0 |
| * | target-tricore: Add instructions of RRR opcode format | Bastian Koppelmann | 2015-01-27 | 4 | -1/+319 |
| * | target-tricore: Add instructions of RRPW opcode format | Bastian Koppelmann | 2015-01-27 | 1 | -0/+70 |
| * | target-tricore: Add instructions of RR2 opcode format | Bastian Koppelmann | 2015-01-27 | 1 | -0/+37 |
| * | target-tricore: Add instructions of RR1 opcode format, that have 0x93 as firs... | Bastian Koppelmann | 2015-01-27 | 1 | -0/+182 |
| * | target-tricore: split up suov32 into suov32_pos and suov32_neg | Bastian Koppelmann | 2015-01-26 | 1 | -15/+26 |
| * | target-tricore: Fix bugs found by coverity | Bastian Koppelmann | 2015-01-26 | 2 | -1/+3 |
| * | target-tricore: calculate av bits before saturation | Bastian Koppelmann | 2015-01-26 | 1 | -12/+16 |
| * | target-tricore: Several translator and cpu model fixes | Bastian Koppelmann | 2015-01-26 | 3 | -4/+5 |
| * | target-tricore: Add missing ULL suffix on 64 bit constant | Peter Maydell | 2015-01-26 | 1 | -1/+1 |
| * | target-tricore: Fix new typos | Stefan Weil | 2015-01-15 | 3 | -4/+4 |
| * | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging | Peter Maydell | 2015-01-09 | 1 | -1/+1 |
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| | * | gen-icount: check cflags instead of use_icount global | Paolo Bonzini | 2015-01-03 | 1 | -1/+1 |
| * | | target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as firs... | Bastian Koppelmann | 2014-12-21 | 3 | -0/+273 |
| * | | target-tricore: Fix MFCR/MTCR insn and B format offset. | Bastian Koppelmann | 2014-12-21 | 2 | -2/+6 |
| * | | target-tricore: Add missing 1.6 insn of BOL opcode format | Bastian Koppelmann | 2014-12-21 | 2 | -1/+54 |
| * | | target-tricore: Add instructions of RR opcode format, that have 0x4b as the f... | Bastian Koppelmann | 2014-12-21 | 4 | -1/+390 |
| * | | target-tricore: Add instructions of RR opcode format, that have 0x1 as the fi... | Bastian Koppelmann | 2014-12-21 | 1 | -0/+97 |
| * | | target-tricore: Add instructions of RR opcode format, that have 0xf as the fi... | Bastian Koppelmann | 2014-12-21 | 3 | -0/+250 |
| * | | target-tricore: Add instructions of RR opcode format, that have 0xb as the fi... | Bastian Koppelmann | 2014-12-21 | 4 | -2/+942 |
| * | | target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32 | Bastian Koppelmann | 2014-12-21 | 1 | -76/+58 |
| * | | target-tricore: Fix mask handling JNZ.T being 7 bit long | Bastian Koppelmann | 2014-12-21 | 1 | -2/+2 |
| * | | target-tricore: pretty-print register dump and show more status registers | Alex Zuepke | 2014-12-21 | 1 | -6/+15 |
| * | | target-tricore: add missing 64-bit MOV in RLC format | Alex Zuepke | 2014-12-21 | 2 | -0/+13 |
| * | | target-tricore: typo in BOL format | Alex Zuepke | 2014-12-21 | 2 | -3/+3 |
| * | | target-tricore: fix offset masking in BOL format | Alex Zuepke | 2014-12-21 | 1 | -1/+1 |
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| * | target-tricore: Add instructions of RCR opcode format | Bastian Koppelmann | 2014-12-10 | 4 | -1/+657 |
