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* target-tricore: Remove the dummy interrupt boilerplateRichard Henderson2014-09-254-8/+0
* target-tricore: Add instructions of SR opcode formatBastian Koppelmann2014-09-013-0/+164
* target-tricore: Add instructions of SLR, SSRO and SRO opcode formatBastian Koppelmann2014-09-011-0/+121
* target-tricore: Add instructions of SC opcode formatBastian Koppelmann2014-09-013-0/+108
* target-tricore: Add instructions of SBR opcode formatBastian Koppelmann2014-09-011-1/+65
* target-tricore: Add instructions of SBC and SBRN opcode formatBastian Koppelmann2014-09-011-0/+36
* target-tricore: Add instructions of SB opcode formatBastian Koppelmann2014-09-013-0/+276
* target-tricore: Add instructions of SRRS and SLRO opcode formatBastian Koppelmann2014-09-011-0/+59
* target-tricore: Add instructions of SSR opcode formatBastian Koppelmann2014-09-011-0/+50
* target-tricore: Add instructions of SRR opcode formatBastian Koppelmann2014-09-013-0/+211
* target-tricore: Add instructions of SRC opcode formatBastian Koppelmann2014-09-012-0/+267
* target-tricore: Add masks and opcodes for decodingBastian Koppelmann2014-09-012-0/+1407
* target-tricore: Add initialization for translation and activate targetBastian Koppelmann2014-09-011-0/+165
* target-tricore: Add softmmu supportBastian Koppelmann2014-09-012-2/+85
* target-tricore: Add target stubs and qom-cpuBastian Koppelmann2014-09-019-0/+916
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