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* target-tricore: Add ftoi and itof instructionsBastian Koppelmann2019-11-291-0/+2
| | | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1457708597-3025-8-git-send-email-kbastian@mail.uni-paderborn.de>
* target-tricore: Add cmp.f instructionBastian Koppelmann2019-11-291-0/+1
| | | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1457708597-3025-7-git-send-email-kbastian@mail.uni-paderborn.de>
* target-tricore: Add div.f instructionBastian Koppelmann2019-11-291-0/+1
| | | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1457708597-3025-6-git-send-email-kbastian@mail.uni-paderborn.de>
* target-tricore: Add mul.f instructionBastian Koppelmann2019-11-291-0/+1
| | | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1457708597-3025-5-git-send-email-kbastian@mail.uni-paderborn.de>
* target-tricore: add add.f/sub.f instructionsBastian Koppelmann2019-11-291-0/+2
| | | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1457708597-3025-4-git-send-email-kbastian@mail.uni-paderborn.de>
* target-tricore: Add trap handling & SOVF/OVF trapsBastian Koppelmann2019-11-291-0/+3
| | | | | | | | | Add the infrastructure needed to generate and handle traps and implement the generation of SOVF and OVF traps. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1455889426-1923-2-git-send-email-kbastian@mail.uni-paderborn.de>
* target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISABastian Koppelmann2015-05-221-0/+2
| | | | | Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: add RR_CRC32 instruction of the v1.6.1 ISABastian Koppelmann2015-05-221-0/+2
| | | | | | | This instruction was introduced by the new Aurix platform. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of SYS opcode formatBastian Koppelmann2015-03-161-0/+3
| | | | | | This adds only the non trap instructions. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as ↵Bastian Koppelmann2015-03-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | first opcode Add helpers helper_subadr_h/_ssov which subs one halfword and adds one halfword, rounds / and saturates each half word independently. Add microcode helper functions: * gen_msubad_h/ads_h: multiply two halfwords left justified and sub from the first one word and add the second one word / and saturate each resulting word independetly. * gen_msubadm_h/adms_h: multiply two halfwords in q-format left justified and sub from the first one word and add to the second one word / and saturate each resulting word independetly. * gen_msubadr32_h/32s_h: multiply two halfwords in q-format left justified and sub from the first one word and add to the second one word, round both results / and saturate each resulting word independetly. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as ↵Bastian Koppelmann2015-03-161-0/+4
| | | | | | | | | | | | | | | | | first opcode Add helpers: * msub64_q_ssov: multiply two 32 bit q-format number, sub the result from a 64 bit q-format number and saturate. * msub32_q_sub_ssov: sub two 64 bit q-format numbers and return a 32 bit result. * msubr_q_ssov: multiply two 32 bit q-format numbers, sub the result from a 32 bit q-format number and saturate. * msubr_q: multiply two 32 bit q-format numbers and sub the result from a 32 bit q-format number. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as ↵Bastian Koppelmann2015-03-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | first opcode Add helpers: * sub64_ssov: subs two 64 bit values and saturates the result. * subr_h/_ssov: subs two halfwords from two words in q-format with rounding / and saturates each result independetly. Add microcode generator: * gen_sub64_d: adds two 64 bit values. * gen_msub_h/s_h: multiply four halfwords, sub each result left justfied from two word values / and saturate each result. * gen_msubm_h/s_h: multiply four halfwords, sub each result left justfied from two words values in q-format / and saturate each result. * gen_msubr32/64_h/s_h: multiply four halfwords, sub each result left justfied from two halftwords/words values in q-format / and saturate each result. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as ↵Bastian Koppelmann2015-03-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | first opcode Add helpers helper_addsur_h/_ssov which adds one halfword and subtracts one halfword, rounds / and saturates each half word independently. Add microcode helper functions: * gen_maddsu_h/sus_h: multiply two halfwords left justified and add to the first one word and subtract from the second one word / and saturate each resulting word independetly. * gen_maddsum_h/sums_h: multiply two halfwords in q-format left justified and add to the first one word and subtract from the second one word / and saturate each resulting word independetly. * gen_maddsur32_h/32s_h: multiply two halfwords in q-format left justified and add to the first one word and subtract from the second one word, round both results / and saturate each resulting word independetly. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as ↵Bastian Koppelmann2015-03-031-0/+4
| | | | | | | | | | | | | | | | | | | | | | | first opcode Add helpers: * madd64_q_ssov: multiply two 32 bit q-format number, add them with a 64 bit q-format number and saturate. * madd32_q_add_ssov: add two 64 bit q-format numbers and return a 32 bit result. * maddr_q_ssov: multiplay two 32 bit q-format numbers, add a 32 bit q-format number and saturate. * maddr_q: multiplay two 32 bit q-format numbers and add a 32 bit q-format number. Note: madd instructions in the q format can behave strange, e.g. 0x1 + (0x80000000 * 0x80000000) << 1 for 32 bit signed values does not cause an overflow on the guest, because all intermediate results should be handled as if they are indefinitely precise. We handle this by inverting the overflow bit for all cases: a + (0x80000000 * 0x80000000) << 1. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as ↵Bastian Koppelmann2015-03-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | first opcode Add helpers: * add64_ssov: adds two 64 bit values and saturates the result. * addr_h/_ssov: adds two halfwords with two words in q-format with rounding / and saturates each result independetly. Add microcode generator: * gen_add64_d: adds two 64 bit values. * gen_addsub64_h: adds/subtracts one halfwords with a word and adds/ subtracts another halftword with another word. * gen_madd_h/s_h: multiply four halfwords, add each result left justfied to two word values / and saturate each result. * gen_maddm_h/s_h: multiply four halfwords, add each result left justfied to two words values in q-format / and saturate each result. * gen_maddr32/64_h/s_h: multiply four halfwords, add each result left justfied to two halftwords/words values in q-format / and saturate each result. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RRR opcode formatBastian Koppelmann2015-01-271-0/+8
| | | | | | | | | | | | | | | | | Add microcode generator function gen_cond_sub. Add helper functions: * ixmax/ixmin: search for the max/min value and its related index in a vector of 16-bit values. * pack: dack two data registers into an IEEE-754 single precision floating point format number. * dvadj: divide-adjust the result after dvstep instructions. * dvstep: divide a reg by a divisor, producing 8-bits of quotient at a time. OPCM_32_RRR_FLOAT -> OPCM_32_RRR_DIVIDE Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as ↵Bastian Koppelmann2014-12-211-0/+4
| | | | | | | | | | | | first opcode Add instructions of RR1 opcode format, that have 0xb3 as first opcode. Add helper functions mulh, mulmh and mulrh, that compute multiplication, with multiprecision (mulmh) or rounding (mulrh) of 4 halfwords, being either low or high parts of two 32 bit regs. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RR opcode format, that have 0x4b as the ↵Bastian Koppelmann2014-12-211-0/+11
| | | | | | | | | | | | | | | | | | first opcode Add instructions of RR opcode format, that have 0x4b as the first opcode. Add helper functions: * parity: Calculates the parity bits for every byte of a 32 int. * bmerge/bsplit: Merges two regs into one bitwise/Splits one reg into two bitwise. * unpack: unpack a IEEE 754 single precision floating point number as exponent and mantissa. * dvinit_b_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation, where the quotient result is guaranteed to fit into 8 bit. * dvinit_h_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation, where the quotient result is guaranteed to fit into 16 bit. OPCM_32_RR_FLOAT -> OPCM_32_RR_DIVIDE. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RR opcode format, that have 0xf as the ↵Bastian Koppelmann2014-12-211-0/+12
| | | | | | | | | | | | | | first opcode Add instructions of RR opcode format, that have 0xf as the first opcode. Add helper functions: * clo/z/s: Counts leading ones/zeros/signs. * clo/z/s_h: Count leading ones/zeros/signs in two haflwords. * sh/_h: Shifts one/two word/hwords. * sha/_h: Shifts one/two word/hwords arithmeticly. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RR opcode format, that have 0xb as the ↵Bastian Koppelmann2014-12-211-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | first opcode Add instructions of RR opcode format, that have 0xb as the first opcode. Add helper functions, for hword and byte arithmetics: * add_h_ssov/suov: Add two halfword and saturate on overflow. * sub_h_ssov/suov: Sub two halfword and saturate on overflow. * absdif_h_ssov: Compute absolute difference for halfwords and saturate on overflow. * abs_h_ssov/suov: Compute absolute value for two halfwords and saturate on overflow. * abs_b/h: Compute absolute value for four/two bytes/halfwords * absdif_b/h: Compute absolute difference for four/two bytes/halfwords * add_b/h: Add four/two bytes/halfwords. * sub_b/h: Sub four/two bytes/halfwords. * eq_b/h: Compare four/two bytes/halfwords with four/two bytes/halfwords on equality and set all bits of to either one ore zero. * eqany_b/h: Compare four/two bytes/halfwords with four/two bytes/halfwords on equality. * lt_b/bu/h/hu: Compare four/two bytes/halfwords with four/two bytes/halfwords on less than signed and unsigned. * max_b/bu/h/hu: Calculate max for four/two bytes/halfwords signed and unsigned. * min_b/bu/h/hu: Calculate min for four/two bytes/halfwords signed and unsigned. Add helper function abs_ssov, that computes the absolute value for a 32 bit integer and saturates on overflow. Add microcode generator functions: * gen_sub_CC: Caluclates sub and sets the carry bit. * gen_subc_CC: Caluclates sub and carry and sets the carry bit * gen_abs: Compute absolute value for a 32 bit integer. * gen_cond_w: Compares two 32 bit values on cond and sets result either zero or all bits one. OPC2_32_RR_MIN switched with OPC2_32_RR_MIN_U. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RCR opcode formatBastian Koppelmann2014-12-101-0/+8
| | | | | | | | | | | Add instructions of RCR opcode format. Add helper for madd32/64_ssov and madd32/64_suov. Add helper for msub32/64_ssov and msub32/64_suov. Add microcode generator function madd/msub for 32bit and 64bit, which calculate a mul and a add/sub. OPC2_32_RCR_MSUB_U_32 -> OPC2_32_RCR_MSUB_U_32. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RLC opcode formatBastian Koppelmann2014-12-101-0/+3
| | | | | | | | | Add instructions of RLC opcode format. Add helper psw_write/read. Add microcode generator gen_mtcr/mfcr, which loads/stores a value to a core special function register, which are defined in csfr.def Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RC opcode formatBastian Koppelmann2014-12-101-0/+6
| | | | | | | | | | | | | | | | | | | | Add instructions of RC opcode format. Add helper for mul, sha, absdif with signed saturation on overflow. Add helper for add, sub, mul with unsigned saturation on overflow. Add microcode generator functions: * gen_add_CC, which calculates the carry bit. * gen_addc_CC, which adds the carry bit to the add and calculates the carry bit. * gen_absdif, which calculates the absolute difference. * gen_mul_i64s/u, which mul two 32 bits val into one 64bit reg. * gen_sh_hi, which shifts two 16bit words in one reg. * gen_sha_hi, which does a arithmetic shift on two 16bit words. * gen_sh_cond, which shifts left a reg by one and writes the result of cond into the lsb. * gen_accumulating_cond, which ands/ors/xors the result of cond of the lsbs with the lsb of the result. * gen_eqany_bi/hi, which checks ever byte/hword on equality. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of BO opcode formatBastian Koppelmann2014-10-201-0/+3
| | | | | | | | | | | Add instructions of BO opcode format. Add microcode generator functions gen_swap, gen_ldmst. Add microcode generator functions gen_st/ld_preincr, which write back the address after the memory access. Add helper for circular and bit reverse addr mode calculation. Add sign extended bitmask for BO_OFF10 field. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of ABS, ABSB opcode formatBastian Koppelmann2014-10-201-0/+4
| | | | | | | | | | Add instructions of ABS, ABSB opcode format. Add microcode generator functions for ld/st of two 32bit reg as one 64bit value. Add microcode generator functions for ldmst and swap. Add helper ldlcx, lducx, stlcx and stucx. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of SR opcode formatBastian Koppelmann2014-09-011-0/+1
| | | | | | | | | | Add instructions of SR opcode format. Add micro-op generator functions for saturate. Add helper return from exception (rfe). Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-id: 1409572800-4116-16-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-tricore: Add instructions of SC opcode formatBastian Koppelmann2014-09-011-0/+1
| | | | | | | | | Add instructions of SC opcode format. Add helper for begin interrupt service routine. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-id: 1409572800-4116-14-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-tricore: Add instructions of SB opcode formatBastian Koppelmann2014-09-011-0/+3
| | | | | | | | | | | Add instructions of SB opcode format. Add helper call/ret. Add micro-op generator functions for branches. Add makro to generate helper functions. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-id: 1409572800-4116-11-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-tricore: Add instructions of SRR opcode formatBastian Koppelmann2014-09-011-0/+4
| | | | | | | | | Add instructions of SRR opcode format. Add helper for add/sub_ssov. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-id: 1409572800-4116-8-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-tricore: Add instructions of SRC opcode formatBastian Koppelmann2014-09-011-0/+16
| | | | | | | | | | | Add instructions of SRC opcode format. Add micro-op generator functions for add, conditional add/sub and shi/shai. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1409572800-4116-7-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-tricore: Add target stubs and qom-cpuBastian Koppelmann2014-09-011-0/+0
Add TriCore target stubs, and QOM cpu, and Maintainer Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-id: 1409572800-4116-2-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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