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* Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20151007' into stagingPeter Maydell2015-10-082-45/+14
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do away with TB retranslation # gpg: Signature made Wed 07 Oct 2015 10:42:08 BST using RSA key ID 4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" * remotes/rth/tags/pull-tcg-20151007: (26 commits) tcg: Adjust CODE_GEN_AVG_BLOCK_SIZE tcg: Check for overflow via highwater mark tcg: Allocate a guard page after code_gen_buffer tcg: Emit prologue to the beginning of code_gen_buffer tcg: Remove tcg_gen_code_search_pc tcg: Remove gen_intermediate_code_pc tcg: Save insn data and use it in cpu_restore_state_from_tb tcg: Pass data argument to restore_state_to_opc tcg: Add TCG_MAX_INSNS target-*: Drop cpu_gen_code define tcg: Merge cpu_gen_code into tb_gen_code target-sparc: Add npc state to insn_start target-sparc: Remove gen_opc_jump_pc target-sparc: Split out gen_branch_n target-sparc: Tidy gen_branch_a interface target-cris: Mirror gen_opc_pc into insn_start target-sh4: Add flags state to insn_start target-s390x: Add cc_op state to insn_start target-mips: Add delayed branch state to insn_start target-i386: Add cc_op state to insn_start ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-071-37/+4
| | | | | | | | | | | | | | | | | | | | It is no longer used, so tidy up everything reached by it. This includes the gen_opc_* arrays, the search_pc parameter and the inline gen_intermediate_code_internal functions. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Pass data argument to restore_state_to_opcRichard Henderson2015-10-071-2/+3
| | | | | | | | | | | | | | | | | | | | The gen_opc_* arrays are already redundant with the data stored in the insn_start arguments. Transition restore_state_to_opc to use data from the latter. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-071-0/+3
| | | | | | | | | | | | | | | | Adjust all translators to respect it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-*: Drop cpu_gen_code defineRichard Henderson2015-10-071-1/+0
| | | | | | | | | | | | | | | | This symbol no longer exists. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-071-1/+2
| | | | | | | | | | | | | | | | This does tidy the icount test common to all targets. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-071-4/+2
| | | | | | | | | | | | | | | | | | | | While we're at it, emit the opcode adjacent to where we currently record data for search_pc. This puts gen_io_start et al on the "correct" side of the marker. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Rename debug_insn_start to insn_startRichard Henderson2015-10-071-1/+1
| | | | | | | | | | | | | | | | With an eye toward making it mandatory. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-tilegx: Support iret instruction and related special registersChen Gang2015-10-074-1/+38
| | | | | | | | | | | | | | | | | | EX_CONTEXT_0_0 is used for jumping address, and EX_CONTEXT_0_1 is for INTERRUPT_CRITICAL_SECTION, which should only be 0 or 1 in user mode, or it will cause target SIGILL (and the patch doesn't support system mode). Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-tilegx: Use TILEGX_EXCP_OPCODE_UNKNOWN and ↵Chen Gang2015-10-071-17/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TILEGX_EXCP_OPCODE_UNIMPLEMENTED correctly For some cases, they are for TILEGX_EXCP_OPCODE_UNKNOWN, not for TILEGX_EXCP_OPCODE_UNIMPLEMENTED. Also for some cases, they are for TILEGX_EXCP_OPCODE_UNIMPLEMENTED, not for TILEGX_EXCP_OPCODE_UNKNOWN. When analyzing issues, the correct printing information is necessary, e.g. grep UIMP in gcc testsuite output log for finding qemu tilegx umimplementation issues, grep UNKNOWN for finding unknown instructions. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-tilegx: Implement v2mults instructionChen Gang2015-10-073-0/+20
| | | | | | | | | | | | Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443956491-26850-3-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-tilegx: Implement v?int_* instructions.Chen Gang2015-10-073-0/+67
| | | | | | | | | | | | Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443956491-26850-2-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-tilegx: Implement v2sh* instructionsChen Gang2015-10-071-1/+17
| | | | | | | | | | | | | | | | It is just according to v1sh* instructions implementation. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443956491-26850-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-tilegx: Handle nofault prefetch instructionsRichard Henderson2015-10-071-14/+26
| | | | | | | | | | | | | | | | These are mapped onto some of the normal load instructions, when the destination is the zero register. Other load insns do fault even when targeting the zero register. Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-tilegx: Fix a typo for mnemonic about "ld_add"Chen Gang2015-10-071-1/+1
| | | | | | | | | | | | Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443562720-3008-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGVRichard Henderson2015-10-072-3/+7
| | | | | | | | | | | | Consolidate signal handling under a single exception. Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-tilegx: Decode ill pseudo-instructionsChen Gang2015-10-072-15/+71
| | | | | | | | | | | | | | | | | | | | | | | | Notice raise and bpt, decoding the constants embedded in the nop addil instruction in the x0 slot. [rth: Generalize TILEGX_EXCP_OPCODE_ILL to TILEGX_EXCP_SIGNAL. Drop validation of signal values.] Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443243635-4886-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-tilegx: Let x1 pipe process bpt instruction onlyChen Gang2015-10-071-1/+7
| | | | | | | | | | | | | | | | According to the related document, bpt can be only in x1 pipe. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443224574-2718-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-tilegx: Implement complex multiply instructionsRichard Henderson2015-10-073-1/+73
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-tilegx: Implement table index instructionsRichard Henderson2015-10-071-0/+15
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-tilegx: Implement crc instructionsRichard Henderson2015-10-073-1/+28
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-tilegx: Implement v1multu instructionChen Gang2015-10-073-0/+18
| | | | | | | | | | | | | | Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1442874414-3578-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-tilegx: Implement v*add and v*sub instructionsChen Gang2015-10-071-21/+116
| | | | | | | | | | | | | | | | [rth: Implement everything inline; handle v1addi and v2addi as well.] Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1442873918-3394-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-tilegx: Implement v*shl, v*shru, and v*shrs instructionsChen Gang2015-10-073-0/+73
| | | | | | | | | | | | | | | | | | v2sh* are implemented with helper functions; v4sh* are implmeneted with inline code. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1442872055-2836-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-tilegx: Tidy simd_helper.cRichard Henderson2015-10-071-4/+7
|/ | | | | | | | Using the V1 macro when we want to replicate a byte across the 8 elements of the word. Using deposit and extract for manipulating specific elements. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle v1shl, v1shru, v1shrsRichard Henderson2015-09-154-2/+76
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle v1shli, v1shruiRichard Henderson2015-09-151-0/+14
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle v4int_l/hRichard Henderson2015-09-151-0/+8
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle atomic instructionsRichard Henderson2015-09-152-2/+82
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle mtspr, mfsprRichard Henderson2015-09-151-3/+73
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle v1cmpeq, v1cmpneRichard Henderson2015-09-151-0/+51
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle mask instructionsRichard Henderson2015-09-151-2/+9
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle scalar multiply instructionsRichard Henderson2015-09-151-0/+112
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle conditional move instructionsRichard Henderson2015-09-151-1/+8
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle shift instructionsRichard Henderson2015-09-151-2/+54
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle bitfield instructionsRichard Henderson2015-09-151-0/+74
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Implement system and memory management instructionsRichard Henderson2015-09-151-23/+54
| | | | | | | Most of which are either nops or exceptions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle comparison instructionsRichard Henderson2015-09-151-6/+33
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle conditional branch instructionsRichard Henderson2015-09-151-13/+38
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle unconditional jump instructionsRichard Henderson2015-09-151-17/+41
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle post-increment load and store instructionsRichard Henderson2015-09-151-8/+86
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle basic load and store instructionsRichard Henderson2015-09-151-15/+115
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle most bit manipulation instructionsRichard Henderson2015-09-153-1/+79
| | | | | | | The crc instructions are omitted from this set. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle arithmetic instructionsRichard Henderson2015-09-151-6/+90
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Handle simple logical operationsRichard Henderson2015-09-151-3/+96
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Add TILE-Gx building filesChen Gang2015-09-151-0/+1
| | | | | | | | | | Add related configuration and make files for tilegx. The target can now build, though not run anything. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <BLU436-SMTP1588E5A03AD5E94B07E988B9660@phx.gbl> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Generate SEGV properlyRichard Henderson2015-09-152-1/+6
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Framework for decoding bundlesRichard Henderson2015-09-151-0/+1145
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Add several helpers for instructions translationChen Gang2015-09-152-0/+74
| | | | | | | | | | The related instructions are exception, cntlz, cnttz, shufflebytes. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <BLU436-SMTP83F96FD8422BE49AFDC9DFB9660@phx.gbl> [rth: Remove incorrect implementation of add_saturate.] Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Add cpu basic features for linux-userChen Gang2015-09-152-0/+345
| | | | | | | | | It implements minimized cpu features for linux-user. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <BLU436-SMTP114819BB03D853801AA9C3CB9660@phx.gbl> Signed-off-by: Richard Henderson <rth@twiddle.net>
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