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* Revert "Get rid of _t suffix"Anthony Liguori2009-10-013-37/+37
| | | | | | | | | | | | In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Get rid of _t suffixmalc2009-10-013-37/+37
| | | | | | | Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
* sparc64-8bit-asiIgor V. Kovalenko2009-09-232-0/+6
| | | | | | | | | | | | | Sparc64 alternate space load/store helpers expect 8 bit ASI value, while wrasi implementation sign-extends ASI operand causing for example 0x80 to appear as 0xFFFFFF80. Resulting value falls out of switch in helpers and causes obscure load/store faults. - correct wrasi by masking lower 8 bits of xor result - use lower 8 bits of ASI register in helpers Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Fix sys-queue.h conflict for goodBlue Swirl2009-09-121-2/+2
| | | | | | | | | | | | | | | Problem: Our file sys-queue.h is a copy of the BSD file, but there are some additions and it's not entirely compatible. Because of that, there have been conflicts with system headers on BSD systems. Some hacks have been introduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896, f40d753718c72693c5f520f0d9899f6e50395e94, 96555a96d724016e13190b28cffa3bc929ac60dc and 3990d09adf4463eca200ad964cc55643c33feb50 but the fixes were fragile. Solution: Avoid the conflict entirely by renaming the functions and the file. Revert the previous hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signalNathan Froyd2009-08-241-0/+1
| | | | | | | | | | | | | | | handle_cpu_signal is very nearly copy-paste code for each target, with a few minor variations. This patch sets up appropriate defaults for a generic handle_cpu_signal and provides overrides for particular targets that did things differently. Fixing things like the persistent (XXX: use sigsetjmp) should now become somewhat easier. Previous comments on this patch suggest that the "activate soft MMU for this block" comments refer to defunct functionality. I have removed such blocks for the appropriate targets in this patch. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* sparc32 remove an unnecessary cpu irq setBlue Swirl2009-08-221-35/+30
| | | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc32/64: fix jmpl followed by branchBlue Swirl2009-08-221-0/+2
| | | | | | | Fix a case where 'jmpl' instruction followed by a branch instruction was handled incorrectly. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc32/64: Fix user emulator breakageBlue Swirl2009-08-181-1/+1
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Fix desynchronization of condition code state when a memory access trapsBlue Swirl2009-08-151-0/+11
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc64: replace tsptr with helper routineIgor Kovalenko2009-08-045-39/+68
| | | | | | | | | | | | | | | | | | | tl and tsptr of members sparc64 cpu state must be changed simultaneously to keep trap state window in sync with current trap level. Currently translation of store to tl does not change tsptr, which leads to corrupt trap state on corresponding trap level. This patch removes tsptr from sparc64 cpu state and replaces all uses with call to helper routine. Changes v0->v1: - reimplemented helper routine with tcg generator - on cpu reset trap type and pstate are populated with power-on reset values, including tl=maxtl Signed-off-by: igor.v.kovalenko@gmail.com Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc64 flush pending conditional evaluations before exposing cpu stateIgor Kovalenko2009-07-311-0/+5
| | | | | | | | | | | | | If translation block is interrupted by e.g. mmu exception we need to compute conditional flags for inclusion into saved cpu state. Otherwise after return from trap conditional instructions would use stale psr/xcc data. Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
* rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIANJuan Quintela2009-07-271-1/+1
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* sparc64 really implement itlb/dtlb automatic replacement writesIgor Kovalenko2009-07-273-90/+84
| | | | | | | | | | | | | | | | | - implement "used" bit in tlb translation entry - mark tlb entry used if qemu code/data translation succeeds - fold i/d mmu replacement writes code into replace_tlb_1bit_lru which adds 1bit lru replacement algorithm; previously code tried to replace first unlocked entry only - extract more bitmasks to named macros - add "immu" or "dmmu" type name to debugging output where appropriate Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
* sparc64 name mmu registers and general cleanupIgor Kovalenko2009-07-274-111/+225
| | | | | | | | | | | | | | | | | | | - add names to mmu registers, this helps understanding the code which uses/modifies them. - fold i/d mmu tlb entries tag and tte arrays into arrays of tlb entries - extract demap_tlb routine (code duplication) - extract replace_tlb routine (code duplication) - flush qemu tlb translations when replacing sparc64 mmu tlb entries I have no test case which demands flushing qemu translations, and this patch should have no other visible changes to runtime. Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
* Fix most warnings (errors with -Werror) when debugging is enabledBlue Swirl2009-07-202-15/+19
| | | | | | | I used the following command to enable debugging: perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * */* */*/* Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Update to a hopefully more future proof FSF addressBlue Swirl2009-07-162-4/+2
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc64: trap handling correctionsIgor Kovalenko2009-07-124-25/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl<blauwirbel@gmail.com> wrote: > On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote: >> Good trap handling is required to process interrupts. >>  This patch fixes the following: >> >>  - sparc64 has no wim register >>  - sparc64 has no psret register, use IE bit of pstate >>   extract IE checking code to cpu_interrupts_enabled >>  - alternate globals are not available if cpu has GL feature >>   in this case bit AG of pstate is constant zero >>  - write to pstate must actually write pstate >>   even if cpu has GL feature >> >>  Also timer interrupt is handled using do_interrupt. > > A bit too much for one patch. Please also remove the code instead of > commenting out. I now excluded timer interrupt related part. To my mind other changes are essentially tied together. > PUT_PSR for Sparc64 needs CC_OP = CC_OP_FLAGS; like Sparc32. Fixed, please find attached the updated version. -- Kind regards, Igor V. Kovalenko
* sparc64: fix helper_st_asi little endian case typoIgor Kovalenko2009-07-121-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Sun, Jul 12, 2009 at 12:43 AM, Stuart Brady<sdbrady@ntlworld.com> wrote: > On Sat, Jul 11, 2009 at 10:22:18PM +0400, Igor Kovalenko wrote: >> It is clear that intention is to byte-swap value to be written, not >> the target address. > > @@ -1949,13 +1949,13 @@ void helper_st_asi(target_ulong addr, ta >     case 0x89: // Secondary LE >         switch(size) { >         case 2: > -            addr = bswap16(addr); > +            addr = bswap16(val); >             ^^^^ > Shouldn't that be 'val = bswap16(val)' (and likewise for the 32-bit and > 64-bit cases)?  Also needs a 'signed-off-by:'... > > Cheers, > -- > Stuart Brady > Thanks, that part I did not runtime-tested. Not sure if those asi stores are of any use for user-mode emulator. Please find attached the corrected version. Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
* sparc64: unify mmu tag matching codeIgor Kovalenko2009-07-121-44/+57
| | | | | | | | | | | This patch extracts common part of sparc64 tag matching code used by IMMU and DMMU lookups. Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
* sparc64: mmu bypass mode correctionIgor Kovalenko2009-07-121-3/+11
| | | | | | | | | | | This Implement physical address truncation in mmu bypass mode. IMMU bypass is also active when cpu enters RED_STATE Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
* Use correct type for SPARC cpu_cc_opPaul Brook2009-06-061-1/+2
| | | | Signed-off-by: Paul Brook <paul@codesourcery.com>
* Convert machine registration to use module init functionsAnthony Liguori2009-05-211-22/+0
| | | | | | This cleans up quite a lot of #ifdefs, extern variables, and other ugliness. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Hardware convenience libraryPaul Brook2009-05-191-2/+0
| | | | | | | | | | | | | | The only target dependency for most hardware is sizeof(target_phys_addr_t). Build these files into a convenience library, and use that instead of building for every target. Remove and poison various target specific macros to avoid bogus target dependencies creeping back in. Big/Little endian is not handled because devices should not know or care about this to start with. Signed-off-by: Paul Brook <paul@codesourcery.com>
* Include assert.h from qemu-common.hPaul Brook2009-05-131-1/+0
| | | | | | | Include assert.h from qemu-common.h and remove other direct uses. cpu-all.h still need to include it because of the dyngen-exec.h hacks Signed-off-by: Paul Brook <paul@codesourcery.com>
* Replace gcc variadic macro extension with C99 versionBlue Swirl2009-05-131-8/+8
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Convert mulsccBlue Swirl2009-05-101-131/+2
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Convert udiv/sdivBlue Swirl2009-05-102-19/+31
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Convert tagged opsBlue Swirl2009-05-102-129/+85
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Convert subxBlue Swirl2009-05-102-31/+50
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Convert subBlue Swirl2009-05-102-37/+83
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Convert logical operations and umul/smulBlue Swirl2009-05-102-24/+43
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Convert addxBlue Swirl2009-05-102-31/+50
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Convert addBlue Swirl2009-05-102-21/+99
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Use dynamical computation for condition codesBlue Swirl2009-05-105-24/+196
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Optimize cmp x, 0 caseBlue Swirl2009-05-031-14/+19
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* ReindentBlue Swirl2009-05-031-319/+312
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Improve instruction name comments for easier searchingBlue Swirl2009-05-021-44/+44
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Clarify: dmmuregs[1] is not a typoBlue Swirl2009-05-021-0/+1
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Optimize operations with immediate parametersBlue Swirl2009-05-021-52/+200
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* Fix Sparc64 sign extension problemsBlue Swirl2009-05-021-32/+36
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc64 fix context value for ITLB faultIgor Kovalenko2009-04-281-1/+1
| | | | | | | Revert previous change to get_physical_address_code: I/D MMU context register is shared, so using dmmuregs[1] is correct Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
* sparc64 fix TLB match codeIgor Kovalenko2009-04-271-7/+7
| | | | | | | | | | | | | | TLB match code must respect page size, otherwise 4M page mappings may be not found. Also correct a typo in get_physical_address_code which should use IMMU registers. Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> -- Kind regards, Igor V. Kovalenko
* Fix a warning in sparc64-linux-user buildBlue Swirl2009-04-251-1/+1
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* sparc64 support TSB related MMU registersIgor Kovalenko2009-04-251-6/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Posting updated patch to the list... >>> On Fri, Apr 24, 2009 at 9:42 PM, Blue Swirl <blauwirbel@gmail.com> wrote: >>>  > >>>  > Nice, though I didn't notice any visible improvement in my tests. >>> >>> This early in boot process there is not much to output; and I test >>>  recent kernel which may use different startup sequence. >>>  I modified openbios cif handler to output arguments and I now can see >>>  visible difference. >>> >>> >>>  > >>>  > About the patch, there are a few problems: >>>  > - it breaks Sparc32 >>> >>> You mean it stops working? >> >> Does not even build. Fixed now. >>>  > - commented out code is ugly >>>  > - if and else should be on the same line as '{' or '}' >>>  > - long lines should be wrapped >>>  > - in the line: >>>  > +    return (((tag_access_register & 0x1fff)<<48)|(tag_access_register >> 22)); >>>  >  there should be white space between ) and << and 48. >>>  > >>> >> >> Also the ")|(" in between is crowded. >> >> Maybe the coding style does not describe this well enough. BTW Supplying indent template would be great. Please see the updated patch qemu-sparc64-tsb-asi-2.patch attached. -- Kind regards, Igor V. Kovalenko
* qemu: introduce qemu_init_vcpu (Marcelo Tosatti)aliguori2009-04-241-0/+1
| | | | | | | | Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
* qemu: per-arch cpu_has_work (Marcelo Tosatti)aliguori2009-04-241-1/+8
| | | | | | | | | | Blue Swirl: fix Sparc32 breakage Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7238 c046a42c-6fe2-441c-8c8c-71466251a162
* Add new command line option -singlestep for tcg single stepping.aurel322009-04-051-1/+1
| | | | | | | | | | | | | | This replaces a compile time option for some targets and adds this feature to targets which did not have a compile time option. Add monitor command to enable or disable single step mode. Modify monitor command "info status" to display single step mode. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7004 c046a42c-6fe2-441c-8c8c-71466251a162
* Delete some unused macros detected with -Wp,-Wunused-macros useblueswir12009-03-163-24/+3
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6856 c046a42c-6fe2-441c-8c8c-71466251a162
* The _exit syscall is used for both thread termination in NPTL applications,pbrook2009-03-071-1/+2
| | | | | | | | | | | | | and process termination in legacy applications. Try to guess which we want based on the presence of multiple threads. Also implement locking when modifying the CPU list. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6735 c046a42c-6fe2-441c-8c8c-71466251a162
* Turn MMUs and caches off on resetblueswir12009-02-211-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6636 c046a42c-6fe2-441c-8c8c-71466251a162
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